[llvm] [RISCV] Add scheduling info for Zcmp (PR #82719)
Visoiu Mistrih Francis via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 23 10:24:15 PST 2024
https://github.com/francisvm updated https://github.com/llvm/llvm-project/pull/82719
>From cf175c5418af53dca9118161e1dede0667ccc616 Mon Sep 17 00:00:00 2001
From: Francis Visoiu Mistrih <francisvm at apple.com>
Date: Thu, 22 Feb 2024 17:18:27 -0800
Subject: [PATCH] [RISCV] Add scheduling info for Zcmp
The order of the entries in the list is:
outs, Defs, implicit-defs, ins, Uses, implicit uses, where the implicit
ones are added programatically during codegen depending on the registers
saved/restored and are not described in the TD files.
This also fixes CM_MVSA01's Defs/Uses list.
---
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td | 32 +++++++++++----
llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir | 49 +++++++++++++++++++++++
2 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index a3ec2e5667ee58..2c8451c5c4ceb2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -181,29 +181,47 @@ def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
// Zcmp
let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
- Defs = [X10, X11], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Defs = [X10, X11] in
def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
- (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">;
+ (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
+ Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
+let Uses = [X10, X11] in
def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
- (ins), "cm.mvsa01", "$rs1, $rs2">;
+ (ins), "cm.mvsa01", "$rs1, $rs2">,
+ Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
} // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp] in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in
-def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push">;
+def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push">,
+ Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
+ ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
+ ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
+ ReadStoreData, ReadStoreData, ReadStoreData]>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
Uses = [X2], Defs = [X2] in
-def CM_POPRET : RVInstZcCPPP<0b11110, "cm.popret">;
+def CM_POPRET : RVInstZcCPPP<0b11110, "cm.popret">,
+ Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+ WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+ WriteLDW, WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
Uses = [X2], Defs = [X2, X10] in
-def CM_POPRETZ : RVInstZcCPPP<0b11100, "cm.popretz">;
+def CM_POPRETZ : RVInstZcCPPP<0b11100, "cm.popretz">,
+ Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW,
+ WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+ WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+ ReadIALU]>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
Uses = [X2], Defs = [X2] in
-def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">;
+def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">,
+ Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+ WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+ WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
} // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
let DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt],
diff --git a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir
new file mode 100644
index 00000000000000..5d162fdfca010b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.mir
@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv32 -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK32I %s
+# RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK32ZCMP %s
+# RUN: llc -mtriple=riscv64 -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK64I %s
+# RUN: llc -mtriple=riscv64 -mattr=+zcmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK64ZCMP %s
+
+---
+name: zcmp_mv
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x11, $x10
+ ; CHECK32I-LABEL: name: zcmp_mv
+ ; CHECK32I: liveins: $x11, $x10
+ ; CHECK32I-NEXT: {{ $}}
+ ; CHECK32I-NEXT: $x8 = ADDI $x11, 0
+ ; CHECK32I-NEXT: $x9 = ADDI $x10, 0
+ ; CHECK32I-NEXT: $x10 = ADDI killed $x9, 0
+ ; CHECK32I-NEXT: $x11 = ADDI $x8, 0
+ ; CHECK32I-NEXT: PseudoRET
+ ;
+ ; CHECK32ZCMP-LABEL: name: zcmp_mv
+ ; CHECK32ZCMP: liveins: $x11, $x10
+ ; CHECK32ZCMP-NEXT: {{ $}}
+ ; CHECK32ZCMP-NEXT: $x9, $x8 = CM_MVSA01 implicit $x10, implicit $x11
+ ; CHECK32ZCMP-NEXT: CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11
+ ; CHECK32ZCMP-NEXT: PseudoRET
+ ;
+ ; CHECK64I-LABEL: name: zcmp_mv
+ ; CHECK64I: liveins: $x11, $x10
+ ; CHECK64I-NEXT: {{ $}}
+ ; CHECK64I-NEXT: $x8 = ADDI $x11, 0
+ ; CHECK64I-NEXT: $x9 = ADDI $x10, 0
+ ; CHECK64I-NEXT: $x10 = ADDI killed $x9, 0
+ ; CHECK64I-NEXT: $x11 = ADDI $x8, 0
+ ; CHECK64I-NEXT: PseudoRET
+ ;
+ ; CHECK64ZCMP-LABEL: name: zcmp_mv
+ ; CHECK64ZCMP: liveins: $x11, $x10
+ ; CHECK64ZCMP-NEXT: {{ $}}
+ ; CHECK64ZCMP-NEXT: $x9, $x8 = CM_MVSA01 implicit $x10, implicit $x11
+ ; CHECK64ZCMP-NEXT: CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11
+ ; CHECK64ZCMP-NEXT: PseudoRET
+ $x8 = ADDI $x11, 0
+ $x9 = ADDI $x10, 0
+ $x10 = ADDI killed $x9, 0
+ $x11 = ADDI $x8, 0
+ PseudoRET
+...
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