[llvm] [RISCV] Vector sub (zext, zext) -> sext (sub (zext, zext)) (PR #82455)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 21 10:12:40 PST 2024


================
@@ -12846,21 +12846,43 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineSubOfBoolean(N, DAG))
     return V;
 
+  EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   // fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
   if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
       isNullConstant(N1.getOperand(1))) {
     ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
     if (CCVal == ISD::SETLT) {
-      EVT VT = N->getValueType(0);
       SDLoc DL(N);
       unsigned ShAmt = N0.getValueSizeInBits() - 1;
       return DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0),
                          DAG.getConstant(ShAmt, DL, VT));
     }
   }
 
+  // sub (zext, zext) -> sext (sub (zext, zext))
+  //   where the sum of the extend widths match, and the inner zexts
+  //   add at least one bit.  (For profitability on rvv, we use a
+  //   power of two for both inner and outer extend.)
----------------
topperc wrote:

If the result type is i128, any operation with the i128 element type as either source or dest will get split repeated until it can be scalarized, then the resulting scalar ops with illegal scalar types will get further legalized to XLen. CodeGen will be so bad I'm not sure its worth optimizing.

For other illegal types, they should get promoted to the next power of 2. After that your combine would run again have another chance at it. So it might be fine to check for legal types?

https://github.com/llvm/llvm-project/pull/82455


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