[llvm] 8ca351d - [ConstraintElim] Add pre-commit tests for PR82271. NFC. (#82357)
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Tue Feb 20 07:28:10 PST 2024
Author: Yingwei Zheng
Date: 2024-02-20T23:28:05+08:00
New Revision: 8ca351d394290f934c2a50293712d4eddf6a97e9
URL: https://github.com/llvm/llvm-project/commit/8ca351d394290f934c2a50293712d4eddf6a97e9
DIFF: https://github.com/llvm/llvm-project/commit/8ca351d394290f934c2a50293712d4eddf6a97e9.diff
LOG: [ConstraintElim] Add pre-commit tests for PR82271. NFC. (#82357)
This patch adds some tests for
https://github.com/llvm/llvm-project/pull/82344.
Added:
llvm/test/Transforms/ConstraintElimination/sext.ll
Modified:
llvm/test/Transforms/ConstraintElimination/minmax.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/ConstraintElimination/minmax.ll b/llvm/test/Transforms/ConstraintElimination/minmax.ll
index 68513ea10ad0fe..ab3e9f381245be 100644
--- a/llvm/test/Transforms/ConstraintElimination/minmax.ll
+++ b/llvm/test/Transforms/ConstraintElimination/minmax.ll
@@ -601,6 +601,126 @@ else:
ret i32 -1
}
+define i64 @pr82271(i32 %a, i32 %b){
+; CHECK-LABEL: define i64 @pr82271
+; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
+; CHECK-NEXT: ret i64 [[SMAX]]
+; CHECK: else:
+; CHECK-NEXT: ret i64 0
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = sext i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
+ ret i64 %smax
+
+else:
+ ret i64 0
+}
+
+define i64 @pr82271_sext_zext_nneg(i32 %a, i32 %b){
+; CHECK-LABEL: define i64 @pr82271_sext_zext_nneg
+; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
+; CHECK-NEXT: ret i64 [[SMAX]]
+; CHECK: else:
+; CHECK-NEXT: ret i64 0
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = zext nneg i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
+ ret i64 %smax
+
+else:
+ ret i64 0
+}
+
+define i64 @pr82271_zext_nneg(i32 %a, i32 %b){
+; CHECK-LABEL: define i64 @pr82271_zext_nneg
+; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = zext nneg i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
+; CHECK-NEXT: ret i64 [[SMAX]]
+; CHECK: else:
+; CHECK-NEXT: ret i64 0
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = zext nneg i32 %a to i64
+ %sb = zext nneg i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
+ ret i64 %smax
+
+else:
+ ret i64 0
+}
+
+define i64 @pr82271_zext(i32 %a, i32 %b){
+; CHECK-LABEL: define i64 @pr82271_zext
+; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = zext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = zext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
+; CHECK-NEXT: ret i64 [[SMAX]]
+; CHECK: else:
+; CHECK-NEXT: ret i64 0
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = zext i32 %a to i64
+ %sb = zext i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
+ ret i64 %smax
+
+else:
+ ret i64 0
+}
+
declare i32 @llvm.smin.i32(i32, i32)
declare i32 @llvm.smax.i32(i32, i32)
declare i32 @llvm.umin.i32(i32, i32)
diff --git a/llvm/test/Transforms/ConstraintElimination/sext.ll b/llvm/test/Transforms/ConstraintElimination/sext.ll
new file mode 100644
index 00000000000000..ed8dd502b6ef9d
--- /dev/null
+++ b/llvm/test/Transforms/ConstraintElimination/sext.ll
@@ -0,0 +1,218 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s
+
+define i1 @cmp_sext(i32 %a, i32 %b){
+; CHECK-LABEL: define i1 @cmp_sext(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = sext i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %cmp2 = icmp sge i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
+
+define i1 @cmp_sext_positive_increment(i32 %a, i32 %b, i64 %c){
+; CHECK-LABEL: define i1 @cmp_sext_positive_increment(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[POS:%.*]] = icmp sgt i64 [[C]], 0
+; CHECK-NEXT: call void @llvm.assume(i1 [[POS]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], [[C]]
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %pos = icmp sgt i64 %c, 0
+ call void @llvm.assume(i1 %pos)
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = sext i32 %b to i64
+ %add = add nsw i64 %sa, %c
+ %cmp2 = icmp sge i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
+
+define i1 @cmp_sext_sgt(i32 %a, i32 %b){
+; CHECK-LABEL: define i1 @cmp_sext_sgt(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = sext i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %cmp2 = icmp sgt i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
+
+define i1 @cmp_zext_nneg(i32 %a, i32 %b){
+; CHECK-LABEL: define i1 @cmp_zext_nneg(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = zext nneg i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = zext nneg i32 %a to i64
+ %sb = zext nneg i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %cmp2 = icmp sge i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
+
+; Negative tests
+
+define i1 @cmp_sext_unsigned(i32 %a, i32 %b){
+; CHECK-LABEL: define i1 @cmp_sext_unsigned(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = sext i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %cmp2 = icmp uge i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
+
+define i1 @cmp_zext(i32 %a, i32 %b){
+; CHECK-LABEL: define i1 @cmp_zext(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = zext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = zext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = zext i32 %a to i64
+ %sb = zext i32 %b to i64
+ %add = add nsw i64 %sa, 1
+ %cmp2 = icmp sge i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
+
+define i1 @cmp_sext_unknown_increment(i32 %a, i32 %b, i64 %c){
+; CHECK-LABEL: define i1 @cmp_sext_unknown_increment(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
+; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
+; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], [[C]]
+; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
+; CHECK-NEXT: ret i1 [[CMP2]]
+; CHECK: else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %then, label %else
+
+then:
+ %sa = sext i32 %a to i64
+ %sb = sext i32 %b to i64
+ %add = add nsw i64 %sa, %c
+ %cmp2 = icmp sge i64 %sb, %add
+ ret i1 %cmp2
+
+else:
+ ret i1 false
+}
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