[llvm] [AArch64] Fix sched model for TSV110 core. (PR #82343)
Yury Gribov via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 22 00:41:02 PST 2024
https://github.com/yugr updated https://github.com/llvm/llvm-project/pull/82343
>From 15d7f5676a0c347457372c3a0ef6e2bdbe3e1dcd Mon Sep 17 00:00:00 2001
From: Yury Gribov <gribov.yuri at huawei.com>
Date: Tue, 20 Feb 2024 14:13:27 +0300
Subject: [PATCH] [AArch64] Fix sched model for TSV110 core.
Accumulator operand of MADD instruction can be bypassed from another
MUL-like operation. Before this fix bypassing was incorrectly applied to
multiplier operand.
---
llvm/lib/Target/AArch64/AArch64SchedTSV110.td | 6 +-
.../AArch64/HiSilicon/tsv110-forwarding.s | 83 +++++++++++++++++++
2 files changed, 86 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-forwarding.s
diff --git a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
index 0ae9a69fd48265..1c577a25bf7390 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -419,10 +419,10 @@ def : InstRW<[TSV110Wr_12cyc_1MDU], (instregex "^(S|U)DIVWr$")>;
def : InstRW<[TSV110Wr_20cyc_1MDU], (instregex "^(S|U)DIVXr$")>;
def TSV110ReadMAW : SchedReadAdvance<2, [TSV110Wr_3cyc_1MDU]>;
-def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instrs MADDWrrr, MSUBWrrr)>;
+def : InstRW<[TSV110Wr_3cyc_1MDU, ReadIM, ReadIM, TSV110ReadMAW], (instrs MADDWrrr, MSUBWrrr)>;
def TSV110ReadMAQ : SchedReadAdvance<3, [TSV110Wr_4cyc_1MDU]>;
-def : InstRW<[TSV110Wr_4cyc_1MDU, TSV110ReadMAQ], (instrs MADDXrrr, MSUBXrrr)>;
-def : InstRW<[TSV110Wr_3cyc_1MDU, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>;
+def : InstRW<[TSV110Wr_4cyc_1MDU, ReadIM, ReadIM, TSV110ReadMAQ], (instrs MADDXrrr, MSUBXrrr)>;
+def : InstRW<[TSV110Wr_3cyc_1MDU, ReadIM, ReadIM, TSV110ReadMAW], (instregex "(S|U)(MADDL|MSUBL)rrr")>;
def : InstRW<[TSV110Wr_4cyc_1MDU], (instregex "^(S|U)MULHrr$")>;
diff --git a/llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-forwarding.s b/llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-forwarding.s
new file mode 100644
index 00000000000000..207822b618396e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-forwarding.s
@@ -0,0 +1,83 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=tsv110 --instruction-info=0 --resource-pressure=0 --timeline --iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN madd nobypass
+mul x0, x1, x2
+add x0, x0, x1
+add x0, x0, x1
+add x0, x0, x1
+# LLVM-MCA-END
+
+# LLVM-MCA-BEGIN madd bypass
+mul x0, x1, x2
+madd x0, x1, x2, x0
+madd x0, x1, x2, x0
+madd x0, x0, x0, x0
+# LLVM-MCA-END
+
+# CHECK: [0] Code Region - madd nobypass
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 4
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 4
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . mul x0, x1, x2
+# CHECK-NEXT: [0,1] D====eER . add x0, x0, x1
+# CHECK-NEXT: [0,2] D=====eER. add x0, x0, x1
+# CHECK-NEXT: [0,3] D======eER add x0, x0, x1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 mul x0, x1, x2
+# CHECK-NEXT: 1. 1 5.0 0.0 0.0 add x0, x0, x1
+# CHECK-NEXT: 2. 1 6.0 0.0 0.0 add x0, x0, x1
+# CHECK-NEXT: 3. 1 7.0 0.0 0.0 add x0, x0, x1
+# CHECK-NEXT: 1 4.8 0.3 0.0 <total>
+
+# CHECK: [1] Code Region - madd bypass
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 4
+# CHECK-NEXT: Total Cycles: 13
+# CHECK-NEXT: Total uOps: 4
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.31
+# CHECK-NEXT: IPC: 0.31
+# CHECK-NEXT: Block RThroughput: 4.0
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 012
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeER . . mul x0, x1, x2
+# CHECK-NEXT: [0,1] D=eeeeER . . madd x0, x1, x2, x0
+# CHECK-NEXT: [0,2] D==eeeeER . . madd x0, x1, x2, x0
+# CHECK-NEXT: [0,3] D======eeeeER madd x0, x0, x0, x0
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 mul x0, x1, x2
+# CHECK-NEXT: 1. 1 2.0 0.0 0.0 madd x0, x1, x2, x0
+# CHECK-NEXT: 2. 1 3.0 0.0 0.0 madd x0, x1, x2, x0
+# CHECK-NEXT: 3. 1 7.0 0.0 0.0 madd x0, x0, x0, x0
+# CHECK-NEXT: 1 3.3 0.3 0.0 <total>
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