[llvm] [RISCV] Add scheduling info for Zcmp (PR #82719)

[Visoiu Mistrih Francis via llvm-commits]

https://github.com/francisvm updated https://github.com/llvm/llvm-project/pull/82719

>From dfec43861d67642f39e3df130b1bf19022f92d75 Mon Sep 17 00:00:00 2001
From: Francis Visoiu Mistrih <francisvm at apple.com>
Date: Thu, 22 Feb 2024 17:18:27 -0800
Subject: [PATCH] [RISCV] Add scheduling info for Zcmp

The order of the entries in the list is:

outs, Defs, implicit-defs, ins, Uses, implicit uses, where the implicit
ones are added programatically during codegen depending on the registers
saved/restored and are not described in the TD files.

This also fixes CM_MVSA01's Defs/Uses list.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoZc.td | 32 ++++++++++++++++++-----
 llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll   | 13 +++++++++
 2 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index a3ec2e5667ee58..2c8451c5c4ceb2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -181,29 +181,47 @@ def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
 
 // Zcmp
 let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
-    Defs = [X10, X11], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+    hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Defs = [X10, X11] in
 def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
-                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">;
+                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
+                Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
 
+let Uses = [X10, X11] in
 def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
-                            (ins), "cm.mvsa01", "$rs1, $rs2">;
+                            (ins), "cm.mvsa01", "$rs1, $rs2">,
+                Sched<[WriteIALU, WriteIALU, ReadIALU, ReadIALU]>;
 } // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
 
 let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp] in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in
-def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push">;
+def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push">,
+              Sched<[WriteIALU, ReadIALU, ReadStoreData, ReadStoreData,
+                     ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
+                     ReadStoreData, ReadStoreData, ReadStoreData, ReadStoreData,
+                     ReadStoreData, ReadStoreData, ReadStoreData]>;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
     Uses = [X2], Defs = [X2] in
-def CM_POPRET : RVInstZcCPPP<0b11110, "cm.popret">;
+def CM_POPRET : RVInstZcCPPP<0b11110, "cm.popret">,
+                Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+                       WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+                       WriteLDW, WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
     Uses = [X2], Defs = [X2, X10] in
-def CM_POPRETZ : RVInstZcCPPP<0b11100, "cm.popretz">;
+def CM_POPRETZ : RVInstZcCPPP<0b11100, "cm.popretz">,
+                 Sched<[WriteIALU, WriteIALU, WriteLDW, WriteLDW, WriteLDW,
+                        WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+                        WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+                        ReadIALU]>;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
     Uses = [X2], Defs = [X2] in
-def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">;
+def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">,
+             Sched<[WriteIALU, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+                    WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW, WriteLDW,
+                    WriteLDW, WriteLDW, WriteLDW, ReadIALU]>;
 } // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]...
 
 let DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt],
diff --git a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
index 2103c3e60b591c..7fc72e9fefab0e 100644
--- a/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
+++ b/llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
@@ -3,6 +3,9 @@
 ; RUN:   | FileCheck -check-prefixes=CHECK32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK32ZCMP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcmp -verify-machineinstrs \
+; RUN:   -stop-after=riscv-move-merge < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK32ZCMPMIR %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK64I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zcmp -verify-machineinstrs < %s \
@@ -77,6 +80,7 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
 ; CHECK64ZCMP-NEXT:    call func
 ; CHECK64ZCMP-NEXT:    addw a0, s2, s0
 ; CHECK64ZCMP-NEXT:    cm.popret {ra, s0-s2}, 32
+
   %call = call i32 @func(i32 %num, i32 %f)
   %call1 = call i32 @func(i32 %num, i32 %f)
   %res = add i32 %call, %f
@@ -163,3 +167,12 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
   %res = call i32 @func(i32 1, i32 %f)
   ret i32 %res
 }
+
+; CHECK32ZCMPMIR-LABEL: name: zcmp_mv
+; CHECK32ZCMPMIR: $x9, $x8 = CM_MVSA01 implicit $x10, implicit $x11
+; CHECK32ZCMPMIR: CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11
+; CHECK32ZCMPMIR-LABEL: name: not_zcmp_mv
+; CHECK32ZCMPMIR-NOT: CM_MVSA01
+; CHECK32ZCMPMIR-NOT: CM_MVA01S
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK32ZCMPMIR: {{.*}}