[llvm] [AArch64] Lowering of fpmode intrinsics in DAG (PR #80611)

[John Brawn via llvm-commits]

================
@@ -523,6 +523,9 @@ enum Rounding {
 // Bit position of rounding mode bits in FPCR.
 const unsigned RoundingBitsPos = 22;
 
+// Reserved bits should be preserved when modifying FPCR.
+const uint64_t ReservedFPControlBits = 0xfe0fe0f8;
----------------
john-brawn-arm wrote:

This doesn't look right. Looking at the latest architecture reference manual (version J.a) the RES0 bits are 3-7, 14, and 27-63, which would give 0xfffffffff80040f8.

https://github.com/llvm/llvm-project/pull/80611