[llvm] [RISCV] Add scheduling info for Zcmp (PR #82719)

[Craig Topper via llvm-commits]

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@@ -183,27 +183,44 @@ def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
 let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
     Defs = [X10, X11], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
-                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">;
+                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
+                Sched<[ReadIALU, ReadIALU, WriteIALU, WriteIALU]>;
 
 def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
-                            (ins), "cm.mvsa01", "$rs1, $rs2">;
+                            (ins), "cm.mvsa01", "$rs1, $rs2">,
+                Sched<[WriteIALU, WriteIALU, WriteIALU, WriteIALU]>;
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topperc wrote:

This instruction is misdeclared, It should be Uses = [X10, X11] not Defs [X10, X11]. And it should have 2 writes and 2 reads.

https://github.com/llvm/llvm-project/pull/82719