[llvm] [AArch64][SVE] Add intrinsincs to assembly mapping for svpmov (PR #81861)

[via llvm-commits]

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@@ -3610,15 +3621,10 @@ def int_aarch64_sve_extq : AdvSIMD_2VectorArgIndexed_Intrinsic;
 //
 // SVE2.1 - Move predicate to/from vector
 //
-def int_aarch64_sve_pmov_to_pred_lane :
-    DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
-                          [llvm_anyvector_ty, llvm_i32_ty],
-                          [IntrNoMem, ImmArg<ArgIndex<1>>]>;
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Lukacma wrote:

We could, but will it not be better to have split like that, in case when in the future another intrinsic will have same pattern to this one ? 

https://github.com/llvm/llvm-project/pull/81861