[llvm] [RISCV] Add scheduling info for Zcmp (PR #82719)

[Craig Topper via llvm-commits]

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@@ -183,27 +183,44 @@ def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
 let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
     Defs = [X10, X11], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
-                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">;
+                            (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
+                Sched<[ReadIALU, ReadIALU, WriteIALU, WriteIALU]>;
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topperc wrote:

The documentation for says 

```
// List the per-operand types that map to the machine model of an                
// instruction. One SchedWrite type must be listed for each explicit             
// def operand in order. Additional SchedWrite types may optionally be           
// listed for implicit def operands.  SchedRead types may optionally             
// be listed for use operands in order. The order of defs relative to            
// uses is insignificant. This way, the same SchedReadWrite list may             
// be used for multiple forms of an operation. For example, a                    
// two-address instruction could have two tied operands or single                
// operand that both reads and writes a reg. In both cases we have a             
// single SchedWrite and single SchedRead in any order. 
```

Specifically "The order of defs relative to uses is insignificant." So if that's true, I'd much rather have all the Writes before all the Reads.

https://github.com/llvm/llvm-project/pull/82719