[llvm] [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bits. (PR #82227)

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git-clang-format --diff 64790064e82467b43c04a70b6e9873e6939be81f 132158c8a2dd13bd4b9c9a23297a134d4615b627 -- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b259d3e20c..030438a009 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13768,18 +13768,18 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
       if (OpBits == DestBits) {
         // Op is i32, Mid is i8, and Dest is i32.  If Op has more than 24 sign
         // bits, it is already ready.
-        if (NumSignBits > DestBits-MidBits)
+        if (NumSignBits > DestBits - MidBits)
           return Op;
       } else if (OpBits < DestBits) {
         // Op is i32, Mid is i8, and Dest is i64.  If Op has more than 24 sign
         // bits, just sext from i32.
         // FIXME: This can probably be ZERO_EXTEND nneg?
-        if (NumSignBits > OpBits-MidBits)
+        if (NumSignBits > OpBits - MidBits)
           return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
       } else {
         // Op is i64, Mid is i8, and Dest is i32.  If Op has more than 56 sign
         // bits, just truncate to i32.
-        if (NumSignBits > OpBits-MidBits)
+        if (NumSignBits > OpBits - MidBits)
           return DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
       }
     }

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https://github.com/llvm/llvm-project/pull/82227