[llvm] [WIP][AMDGPU] Split `isInlinableLiteral16` into three and call the specific version if possible (PR #81345)

[Shilei Tian via llvm-commits]

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@@ -99,39 +99,39 @@ define i32 @inline_A_constraint_H1() {
 ; VI-LABEL: {{^}}inline_A_constraint_H2:
 ; VI: v_mov_b32 {{v[0-9]+}}, 0x3c00
 define i32 @inline_A_constraint_H2() {
-  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 1.0 to i16))
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(trunc i32 bitcast (float 1.0 to i32) to i16)
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shiltian wrote:

In the test case, `0x3c00` is not inlined *in the encoding* because the operand is `i32` instead of `i16`. However, when we parse the inline asm, the parser can only see `i16` because that's what we tell the parser via the type. Then we have a constraint `A`, so the parser is trying to parse it as a 16-bit inline literal. As for whether eventually it is the inline literal in the encoding, it will only happen after we finish parsing.

`v_mov_b32 {{v[0-9]+}}, 0x3c00` is right but it should not be the intention of this test case because eventually it is not an inline instant. It just "tricks" the inline asm parser to falsely take it as inline literal.

https://github.com/llvm/llvm-project/pull/81345