[llvm] [VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (PR #82627)

[Yeting Kuo via llvm-commits]

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@@ -0,0 +1,233 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \
+; RUN:     -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV32
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yetingk wrote:

Each lane of `vp.lrint` has same behavior as `lrint`. `lrint` return the `long` type. For ilp32* abi, `long` equals to `i32`. 

https://github.com/llvm/llvm-project/pull/82627