[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[Jack Styles via llvm-commits]

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@@ -278,6 +278,14 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
     return &InstrInfo->getRegisterInfo();
   }
 
+  /// Returns true as the ARM Architecture is supported by the Init Undef Pass.
+  /// We want to enable this for MVE and NEON instructions, however this can be
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Stylie777 wrote:

There are currently no NEON instructions that use easy-clobber. There are however early-clobber instructions that might get missed by checking for `HasMVEIntegerOps`. Changed this to `true` as it should run regardless, and all the required register types have been implemented.

https://github.com/llvm/llvm-project/pull/77770