[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -1480,6 +1480,11 @@ static bool IsSVECalleeSave(MachineBasicBlock::iterator I) {
   switch (I->getOpcode()) {
   default:
     return false;
+  case AArch64::PTRUE_C_B:
+  case AArch64::LD1B_2Z_IMM:
+  case AArch64::ST1B_2Z_IMM:
+    return I->getMF()->getSubtarget<AArch64Subtarget>().hasSVE2p1() ||
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momchil-velikov wrote:

Those instructions are already generated. If they were generated in error, how does returning `false` from this function helps?

If we are targeting SVE2.1/SME2, ignoring the `FrameSetup` / `FrameDestroy` flags  and returning `true` will result in a few loops iterating more than needed.
If we are not targeting SVE2.1/SME,  ignoring the `FrameSetup` / `FrameDestroy` flags  and returning `false` will obviously not help with the wrong (for the architecture) instructions, and in addition it would cause said loops to terminate early.

All in all, we will end up emitting various frame setup instructions and directives in the wrong position.

If you want to double check, add an assertion and let the cases fallthough to the existing return.


https://github.com/llvm/llvm-project/pull/77665