[llvm] Fix https://github.com/llvm/llvm-project/issues/75998 (PR #82661)

[Eli Friedman via llvm-commits]

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@@ -369,7 +369,8 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {
 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
   let AltOrders = [(and tcGPR, tGPR)];
   let AltOrderSelect = [{
-      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
+      return MF.getSubtarget<ARMSubtarget>().isThumb1Only() ||
+        MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true);
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efriedma-quic wrote:

This looks like the same check we do in ARMTargetLowering::IsEligibleForTailCallOptimization; can we unify them, so it's clear they're checking the same thing?

https://github.com/llvm/llvm-project/pull/82661