[llvm] [RISCV] Fix scheduling info for C_FSW and C_FSWSP. (PR #82339)

[Visoiu Mistrih Francis via llvm-commits]

================
@@ -368,7 +368,7 @@ def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
 let DecoderNamespace = "RISCV32Only_",
     Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]  in
 def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
-             Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
+             Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
----------------
francisvm wrote:

Good point, should all of these use `ReadFMemBase`/`ReadFStoreData` too?

```
$ ag 'FPR' llvm/lib/Target/RISCV/RISCVInstrInfoC.td
324:def C_FLD  : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
341:def C_FLW  : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
358:def C_FSD  : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
375:def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
518:def C_FLDSP  : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
532:def C_FLWSP  : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
576:def C_FSDSP  : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
590:def C_FSWSP  : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
```

https://github.com/llvm/llvm-project/pull/82339