[llvm] [AMDGPU] Fix decoder for BF16 inline constants (PR #82276)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -1108,54 +1108,64 @@ class RegOrImmOperand <RegisterClass RegClass, string OperandTypeName>
     let ParserMatchClass = RegImmMatcher<!subst("_Deferred", "", NAME)>;
 }
 
+// Should be in sync with the OperandSemantics defined in SIDefines.h
+def OperandSemantics {
+  int INT = 0;
+  int FP16 = 1;
+  int BF16 = 2;
+  int FP32 = 3;
+  int FP64 = 4;
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rampitec wrote:

Right, but really semantics of fp32 and fp64 is different. I also think it may allow some further simplifications in the asm parser and decoder.

https://github.com/llvm/llvm-project/pull/82276