[llvm] [RISCV] Fix scheduling info for C_FSW and C_FSWSP. (PR #82339)
Francesco Petrogalli via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 20 23:29:24 PST 2024
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@@ -368,7 +368,7 @@ def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
let DecoderNamespace = "RISCV32Only_",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
- Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
+ Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
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fpetrogalli wrote:
Done, thank you
https://github.com/llvm/llvm-project/pull/82339
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