[llvm] [DAGCombiner] Preserve nneg flag from inner zext when we combine (z/s/aext (zext X)) (PR #82199)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 19 10:51:51 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/82199
>From 8c4bd863670b256cac9349ceec5f9d8d2159a162 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 18 Feb 2024 17:59:49 -0800
Subject: [PATCH 1/2] [DAGCombiner] Preserve nneg flag from inner zext when we
combine (z/s/aext (zext X))
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 19 ++++++++++-----
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 23 ++++++++++++++-----
2 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2a09e44e192979..91ed3d9bd69317 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13710,8 +13710,12 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
// fold (zext (zext x)) -> (zext x)
// fold (zext (aext x)) -> (zext x)
- if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
- return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
+ if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
+ SDNodeFlags Flags;
+ if (N0.getOpcode() == ISD::ZERO_EXTEND)
+ Flags.setNonNeg(N0->getFlags().hasNonNeg());
+ return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0), Flags);
+ }
// fold (zext (aext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
// fold (zext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
@@ -13985,10 +13989,13 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
// fold (aext (aext x)) -> (aext x)
// fold (aext (zext x)) -> (zext x)
// fold (aext (sext x)) -> (sext x)
- if (N0.getOpcode() == ISD::ANY_EXTEND ||
- N0.getOpcode() == ISD::ZERO_EXTEND ||
- N0.getOpcode() == ISD::SIGN_EXTEND)
- return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
+ if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND ||
+ N0.getOpcode() == ISD::SIGN_EXTEND) {
+ SDNodeFlags Flags;
+ if (N0.getOpcode() == ISD::ZERO_EXTEND)
+ Flags.setNonNeg(N0->getFlags().hasNonNeg());
+ return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Flags);
+ }
// fold (aext (aext_extend_vector_inreg x)) -> (aext_extend_vector_inreg x)
// fold (aext (zext_extend_vector_inreg x)) -> (zext_extend_vector_inreg x)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 421bb516ad242f..add92cf8b31e44 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5715,8 +5715,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
assert(N1.getValueType().bitsLT(VT) && "Invalid sext node, dst < src!");
- if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
- return getNode(OpOpcode, DL, VT, N1.getOperand(0));
+ if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) {
+ SDNodeFlags Flags;
+ if (OpOpcode == ISD::ZERO_EXTEND)
+ Flags.setNonNeg(N1->getFlags().hasNonNeg());
+ return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
+ }
if (OpOpcode == ISD::UNDEF)
// sext(undef) = 0, because the top bits will all be the same.
return getConstant(0, DL, VT);
@@ -5732,8 +5736,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
N1.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!");
assert(N1.getValueType().bitsLT(VT) && "Invalid zext node, dst < src!");
- if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
- return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0));
+ if (OpOpcode == ISD::ZERO_EXTEND) { // (zext (zext x)) -> (zext x)
+ SDNodeFlags Flags;
+ Flags.setNonNeg(N1->getFlags().hasNonNeg());
+ return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
+ }
if (OpOpcode == ISD::UNDEF)
// zext(undef) = 0, because the top bits will be zero.
return getConstant(0, DL, VT);
@@ -5769,9 +5776,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
assert(N1.getValueType().bitsLT(VT) && "Invalid anyext node, dst < src!");
if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
- OpOpcode == ISD::ANY_EXTEND)
+ OpOpcode == ISD::ANY_EXTEND) {
+ SDNodeFlags Flags;
+ if (OpOpcode == ISD::ZERO_EXTEND)
+ Flags.setNonNeg(N1->getFlags().hasNonNeg());
// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
- return getNode(OpOpcode, DL, VT, N1.getOperand(0));
+ return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
+ }
if (OpOpcode == ISD::UNDEF)
return getUNDEF(VT);
>From 6d0c644ab7539713b5900f20ff6bb8af486e87bf Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 19 Feb 2024 10:47:51 -0800
Subject: [PATCH 2/2] fixup! regenerate test.
---
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll | 25 ++++++----------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
index af136806f71845..a41d1ce87a8e2b 100644
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -791,24 +791,13 @@ define void @zext_nneg_dominating_icmp_i32(i16 signext %0) {
; RV32I-NEXT: .LBB47_2:
; RV32I-NEXT: ret
;
-; RV64I-LABEL: zext_nneg_dominating_icmp_i32:
-; RV64I: # %bb.0:
-; RV64I-NEXT: bltz a0, .LBB47_2
-; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: slli a0, a0, 48
-; RV64I-NEXT: srli a0, a0, 48
-; RV64I-NEXT: tail bar_i32
-; RV64I-NEXT: .LBB47_2:
-; RV64I-NEXT: ret
-;
-; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32:
-; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: bltz a0, .LBB47_2
-; RV64ZBB-NEXT: # %bb.1:
-; RV64ZBB-NEXT: zext.h a0, a0
-; RV64ZBB-NEXT: tail bar_i32
-; RV64ZBB-NEXT: .LBB47_2:
-; RV64ZBB-NEXT: ret
+; RV64-LABEL: zext_nneg_dominating_icmp_i32:
+; RV64: # %bb.0:
+; RV64-NEXT: bltz a0, .LBB47_2
+; RV64-NEXT: # %bb.1:
+; RV64-NEXT: tail bar_i32
+; RV64-NEXT: .LBB47_2:
+; RV64-NEXT: ret
%2 = icmp sgt i16 %0, -1
br i1 %2, label %3, label %5
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