[llvm] [RISCV][NFC] Allow SchedVar to be a def inside our scheduler model files. (PR #82634)

[Michael Maitland via llvm-commits]

michaelmaitland wrote:

> Why does `VLDSX0Pred` need to be inside the SiFive7Base class? There's nothing that changes based on which model uses it. It could just be a top level record in RISCVScheduleV.td. ARM, AArch64, and X86 have a SchedPredicates.td file. I don't think we have enough predicates yet to justify that, but my point is that sched predicates can be independent of the model.

`SchedPredicate` class has access to the SchedModel. For example, it would be okay to say:
```
def MyPred : SchedPredicate<[{SchedModel->getSubtargetInfo()->hasFeature(RISCV::TuneMyFeature)}]>;
```
In these cases, the predicate needs to be defined under the `let` statement.

https://github.com/llvm/llvm-project/pull/82634