[llvm] [RISCV] Use predicated FP extension when promoting VP operands (PR #79328)

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``````````bash
git-clang-format --diff 3112578597c031e6f00c4b126182bd0d8582c729 366e3499e405aebd7ca6136986f3a413d79d7605 -- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index ce6dd7603c..85ee41a5b7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -167,7 +167,7 @@ class VectorLegalizer {
   void PromoteFP_TO_INT(SDNode *Node, SmallVectorImpl<SDValue> &Results);
 
   // Promotes the floating-point operand at the given index of the node into
-  // an FP_EXTEND/VP_FP_EXTEND node of type NewVT 
+  // an FP_EXTEND/VP_FP_EXTEND node of type NewVT
   SDValue PromoteFPOperand(SDNode *Node, MVT NewVT, unsigned Index);
 
   /// Implements vector reduce operation promotion.
@@ -573,14 +573,14 @@ bool VectorLegalizer::LowerOperationWrapper(SDNode *Node,
   return true;
 }
 
-SDValue VectorLegalizer::PromoteFPOperand(SDNode *Node, MVT NewVT, 
+SDValue VectorLegalizer::PromoteFPOperand(SDNode *Node, MVT NewVT,
                                           unsigned Index) {
   SDLoc DL(Node);
   if (ISD::isVPOpcode(Node->getOpcode())) {
     auto MaskIdx = *ISD::getVPMaskIdx(Node->getOpcode());
     auto EVLIdx = *ISD::getVPExplicitVectorLengthIdx(Node->getOpcode());
     return DAG.getNode(ISD::VP_FP_EXTEND, DL, NewVT, Node->getOperand(Index),
-                          Node->getOperand(MaskIdx), Node->getOperand(EVLIdx));
+                       Node->getOperand(MaskIdx), Node->getOperand(EVLIdx));
   }
   return DAG.getNode(ISD::FP_EXTEND, DL, NewVT, Node->getOperand(Index));
 }

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https://github.com/llvm/llvm-project/pull/79328