[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,70 @@
+//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+class RISCVProfile<string name, list<SubtargetFeature> features>
+  : SubtargetFeature<name, "RISCVProfile", NAME,
+                     "RISC-V " # name # " profile",
+                     features>;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit]>;
+
+def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit]>;
+
+def RVA20U64 : RISCVProfile<"rva20u64", [Feature64Bit,
+                                         FeatureStdExtM,
+                                         FeatureStdExtA,
+                                         FeatureStdExtF,
+                                         FeatureStdExtD,
+                                         FeatureStdExtC,
+                                         FeatureStdExtZicsr]>;
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topperc wrote:

Zicsr is implied by F

https://github.com/llvm/llvm-project/pull/76357