[llvm] [Mips] mips1 DivByZeroTrap (PR #81311)
YunQiang Su via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 21 02:47:51 PST 2024
================
@@ -206,12 +234,30 @@ entry:
}
define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
-; GP32-LABEL: sdiv_i32:
-; GP32: # %bb.0: # %entry
-; GP32-NEXT: div $zero, $4, $5
-; GP32-NEXT: teq $5, $zero, 7
-; GP32-NEXT: jr $ra
-; GP32-NEXT: mflo $2
+; GP32R0R1-LABEL: sdiv_i32:
+; GP32R0R1: # %bb.0: # %entry
+; GP32R0R1-NEXT: div $zero, $4, $5
+; GP32R0R1-NEXT: bnez $5, $BB3_2
+; GP32R0R1-NEXT: nop
+; GP32R0R1-NEXT: # %bb.1: # %entry
+; GP32R0R1-NEXT: break 0, 7
+; GP32R0R1-NEXT: $BB3_2: # %entry
+; GP32R0R1-NEXT: jr $ra
+; GP32R0R1-NEXT: mflo $2
+;
+; GP32R0R2-LABEL: sdiv_i32:
+; GP32R0R2: # %bb.0: # %entry
+; GP32R0R2-NEXT: div $zero, $4, $5
+; GP32R0R2-NEXT: teq $5, $zero, 7
+; GP32R0R2-NEXT: jr $ra
+; GP32R0R2-NEXT: mflo $2
+;
+; GP32R2R5-LABEL: sdiv_i32:
+; GP32R2R5: # %bb.0: # %entry
+; GP32R2R5-NEXT: div $zero, $4, $5
+; GP32R2R5-NEXT: teq $5, $zero, 7
+; GP32R2R5-NEXT: jr $ra
+; GP32R2R5-NEXT: mflo $2
----------------
wzssyqa wrote:
R0R2 is same with R2R5?
If so, why not merge them?
https://github.com/llvm/llvm-project/pull/81311
More information about the llvm-commits
mailing list