[llvm] [SelectionDAG] Improve isOrEquivalentToAdd (PR #82767)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-loongarch

Author: hev (heiher)

<details>
<summary>Changes</summary>

`SelectionDAGISel::isOrEquivalentToAdd` can only test operands that are directly based on the stack frame. The improvement in this commit is to add a call to `SelectionDAG::haveNoCommonBitsSet` for testing, which helps optimize the code generation for `load (or base, imm)`.

---
Full diff: https://github.com/llvm/llvm-project/pull/82767.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+1-1) 
- (modified) llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll (+1-2) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 9b5ab4267b80e9..0cf9a02af35c49 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4214,7 +4214,7 @@ bool SelectionDAGISel::isOrEquivalentToAdd(const SDNode *N) const {
     // the alignment, then this or is really an add.
     return (Off >= 0) && (((A.value() - 1) & Off) == unsigned(Off));
   }
-  return false;
+  return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
 }
 
 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
diff --git a/llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll b/llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
index 09453004dcef74..ff845cb1f3dbd9 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
@@ -22,8 +22,7 @@ define void @box(ptr noalias nocapture noundef writeonly sret(%Box) align 16 der
 ; CHECK-NEXT:    st.d $a1, $a0, 24
 ; CHECK-NEXT:    ld.d $a1, $a3, 16
 ; CHECK-NEXT:    st.d $a1, $a0, 16
-; CHECK-NEXT:    ori $a1, $a3, 8
-; CHECK-NEXT:    ld.d $a1, $a1, 0
+; CHECK-NEXT:    ld.d $a1, $a3, 8
 ; CHECK-NEXT:    st.d $a1, $a0, 8
 ; CHECK-NEXT:    addi.d $sp, $sp, 96
 ; CHECK-NEXT:    ret

``````````

</details>


https://github.com/llvm/llvm-project/pull/82767