[llvm] clarify semantics of masked vector load/store (PR #82469)

[Nikita Popov via llvm-commits]

nikic wrote:

I would rephrase this in terms of something like this:

> However, these intrinsics behave as-is the masked off lanes are not accessed.

Which should tell use everything necessary about their semantics. Then can continue to clarify that this means no exceptions / data races / etc.

https://github.com/llvm/llvm-project/pull/82469