[llvm] Add ARM:r12 and ARM:LR as scratch regs for ARM (PR #82454)
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Tue Feb 20 18:12:41 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: AtariDreams (AtariDreams)
<details>
<summary>Changes</summary>
r12 is the intra-procedural scratch register and lr is clobbered across every call.
---
Full diff: https://github.com/llvm/llvm-project/pull/82454.diff
2 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+8)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.h (+2)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index b98006ed0cb3f4..91b3b224aa1679 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13789,6 +13789,14 @@ static SDValue PerformADDVecReduce(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+const MCPhysReg *getScratchRegisters(CallingConv::ID) const {
+ // LR is a not a scratch register, but we must treat it as clobbered by any
+ // call site. Hence we include LR in the scratch registers, which are in turn
+ // added as implicit-defs for stackmaps and patchpoints.
+ static const MCPhysReg ScratchRegs[] = {ARM::R12, ARM::LR, 0};
+ return ScratchRegs;
+}
+
bool
ARMTargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
CombineLevel Level) const {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index b13ddf697cb806..bca55b5c95a235 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -738,6 +738,8 @@ class VectorType;
Align getABIAlignmentForCallingConv(Type *ArgTy,
const DataLayout &DL) const override;
+ const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
+
bool isDesirableToCommuteWithShift(const SDNode *N,
CombineLevel Level) const override;
``````````
</details>
https://github.com/llvm/llvm-project/pull/82454
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