[llvm] [SystemZ] Use VT (not ArgVT) for SlotVT in LowerCall(). (PR #82475)
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 21 01:20:56 PST 2024
https://github.com/JonPsson1 created https://github.com/llvm/llvm-project/pull/82475
When an integer argument is promoted and not split (like i72 -> i128 on a new machine with vector support), the SlotVT should be i128, which is stored in VT - not ArgVT.
Fixes #81417
>From c16c1cf20cd8c3e1e2c77c4341cf54c9a50a65d3 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: Wed, 21 Feb 2024 09:29:16 +0100
Subject: [PATCH] [SystemZ] Use VT (not ArgVT) for SlotVT in LowerCall().
---
.../lib/Target/SystemZ/SystemZISelLowering.cpp | 2 +-
llvm/test/CodeGen/SystemZ/frame-29.ll | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/SystemZ/frame-29.ll
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index d92586f7d05d0d..3b85a6ac0371ed 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1923,7 +1923,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
unsigned N = getNumRegistersForCallingConv(Ctx, CLI.CallConv, OrigArgVT);
SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N);
} else {
- SlotVT = Outs[I].ArgVT;
+ SlotVT = Outs[I].VT;
}
SDValue SpillSlot = DAG.CreateStackTemporary(SlotVT);
int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
diff --git a/llvm/test/CodeGen/SystemZ/frame-29.ll b/llvm/test/CodeGen/SystemZ/frame-29.ll
new file mode 100644
index 00000000000000..6cc0d9e985e160
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/frame-29.ll
@@ -0,0 +1,18 @@
+; RUN: llc %s -o - -mtriple=s390x-linux-gnu -mcpu=z16 -print-after=finalize-isel 2>&1 | FileCheck %s
+;
+; Test that the correct space is allocated for the outgoing stack argument.
+
+declare void @bar(i72 %Arg);
+
+define void @foo() {
+; CHECK-LABEL: # Machine code for function foo: IsSSA, TracksLiveness
+; CHECK-NEXT: Frame Objects:
+; CHECK-NEXT: fi#0: size=1, align=2, at location [SP]
+; CHECK-NEXT: fi#1: size=16, align=8, at location [SP]
+
+; CHECK-LABEL: foo:
+; CHECK: aghi %r15, -184
+ %1 = alloca i8, align 2
+ tail call fastcc void @bar(i72 2097168)
+ ret void
+}
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