[lld] [llvm] [Mips] Fix unable to handle inline assembly ends with compat-branch o… (PR #77291)

[YunQiang Su via llvm-commits]

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@@ -2331,6 +2389,14 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
 
   // If this instruction has a delay slot and .set reorder is active,
   // emit a NOP after it.
+  // The format of the third case is:
+  // .set noreorder
+  // bnezc
+  // nop
+  // .set noreorder
+  // j
+  // nop
+  // .set reorder
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wzssyqa wrote:

I think that we should add a test case for the ".set reorder/noreorder" logic.

https://github.com/llvm/llvm-project/pull/77291