[llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)

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git-clang-format --diff 8e22fffc85b36784146041499b716cec74285660 73b8c4ae5924b5154dbe14a41a141e7eff3cf231 -- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86InstrInfo.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index cee1659eb7..d9feae557a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -777,7 +777,7 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() {
 
 #if 0
 #define NOAH_DUMP(v, todo)                                                     \
-  dbgs() << "-------------------- STAGE" << #v << " ---------------------\n";     \
+  dbgs() << "-------------------- STAGE" << #v << " ---------------------\n";  \
   todo;
 #else
 #define NOAH_DUMP(v, todo)
@@ -905,7 +905,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
       CurDAG->VerifyDAGDivergence();
 #endif
 
-  NOAH_DUMP(2, CurDAG->dump());
+    NOAH_DUMP(2, CurDAG->dump());
     {
       NamedRegionTimer T("legalize_types2", "Type Legalization 2", GroupName,
                          GroupDescription, TimePassesIsEnabled);
@@ -925,7 +925,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
     if (ViewDAGCombineLT && MatchFilterBB)
       CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
 
-  NOAH_DUMP(3, CurDAG->dump());
+    NOAH_DUMP(3, CurDAG->dump());
     // Run the DAG combiner in post-type-legalize mode.
     {
       NamedRegionTimer T("combine_lv", "DAG Combining after legalize vectors",
@@ -967,7 +967,6 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   if (ViewDAGCombine2 && MatchFilterBB)
     CurDAG->viewGraph("dag-combine2 input for " + BlockName);
 
-
   NOAH_DUMP(5, CurDAG->dump());
   // Run the DAG combiner in post-legalize mode.
   {
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 889137d4c8..d29f15cb9e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -938,7 +938,6 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts(
                                          Depth);
 }
 
-
 // Attempt to form ext(avgfloor(A, B)) from shr(add(ext(A), ext(B)), 1).
 //      or to form ext(avgceil(A, B)) from shr(add(ext(A), ext(B), 1), 1).
 static SDValue combineShiftToAVG(SDValue Op, SelectionDAG &DAG,
@@ -2475,7 +2474,6 @@ bool TargetLowering::SimplifyDemandedBits(
                              Depth + 1))
       return true;
 
-
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
     assert(Known.getBitWidth() == InBits && "Src width has changed?");
 

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https://github.com/llvm/llvm-project/pull/82290