[llvm] Correctly round FP -> BF16 when SDAG expands such nodes (PR #82399)
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Wed Feb 21 08:19:56 PST 2024
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git-clang-format --diff 2de269a641e4ffbb7a44e559c4c0a91bb66df823 f82d958f0da57c75a8c4b505a0561c8e42d283f4 -- llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 8c7f4111db..d059dc66d0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10946,20 +10946,20 @@ SDValue TargetLowering::expandFP_ROUND(SDNode *Node, SelectionDAG &DAG) const {
Op = DAG.getNode(ISD::BITCAST, dl, I32, Op);
// Extract the sign bit.
- SDValue SignBit = DAG.getNode(
- ISD::AND, dl, I32, Op,
- DAG.getConstant(APInt::getSignMask(32), dl, I32));
+ SDValue SignBit =
+ DAG.getNode(ISD::AND, dl, I32, Op,
+ DAG.getConstant(APInt::getSignMask(32), dl, I32));
// Set the quiet bit.
- SDValue NaN =
- DAG.getNode(ISD::OR, dl, I32, SignBit, DAG.getConstant(0x400000, dl, I32));
+ SDValue NaN = DAG.getNode(ISD::OR, dl, I32, SignBit,
+ DAG.getConstant(0x400000, dl, I32));
// Factor in the contribution of the low 16 bits.
SDValue One = DAG.getConstant(1, dl, I32);
SDValue Lsb = DAG.getNode(ISD::SRL, dl, I32, Op,
DAG.getShiftAmountConstant(16, I32, dl));
Lsb = DAG.getNode(ISD::AND, dl, I32, Lsb, One);
- SDValue RoundingBias = DAG.getNode(
- ISD::ADD, dl, I32, DAG.getConstant(0x7fff, dl, I32), Lsb);
+ SDValue RoundingBias =
+ DAG.getNode(ISD::ADD, dl, I32, DAG.getConstant(0x7fff, dl, I32), Lsb);
SDValue Add = DAG.getNode(ISD::ADD, dl, I32, Op, RoundingBias);
// Don't round if we had a NaN, we don't want to turn 0x7fffffff into
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https://github.com/llvm/llvm-project/pull/82399
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