[llvm] revert type profiling change as it breaks compiler-rt test on non-Linux platforms (PR #82581)
Mingming Liu via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 21 21:38:01 PST 2024
https://github.com/minglotus-6 created https://github.com/llvm/llvm-project/pull/82581
Examples https://lab.llvm.org/buildbot/#/builders/127/builds/62532/steps/8/logs/stdio
```
# | clang_rt.profile-x86_64.lib(InstrProfilingBuffer.c.obj) : error LNK2019: unresolved external symbol __llvm_profile_begin_vtabnames referenced in function __llvm_profile_get_size_for_buffer
# | clang_rt.profile-x86_64.lib(InstrProfilingWriter.c.obj) : error LNK2001: unresolved external symbol __llvm_profile_begin_vtabnames
# | clang_rt.profile-x86_64.lib(InstrProfilingBuffer.c.obj) : error LNK2019: unresolved external symbol __llvm_profile_end_vtabnames referenced in function __llvm_profile_get_size_for_buffer
# | clang_rt.profile-x86_64.lib(InstrProfilingWriter.c.obj) : error LNK2001: unresolved external symbol __llvm_profile_end_vtabnames
# | clang_rt.profile-x86_64.lib(InstrProfilingBuffer.c.obj) : error LNK2019: unresolved external symbol __llvm_profile_begin_vtables referenced in function __llvm_profile_get_size_for_buffer
# | clang_rt.profile-x86_64.lib(InstrProfilingWriter.c.obj) : error LNK2001: unresolved external symbol __llvm_profile_begin_vtables
# | clang_rt.profile-x86_64.lib(InstrProfilingBuffer.c.obj) : error LNK2019: unresolved external symbol __llvm_profile_end_vtables referenced in function __llvm_profile_get_size_for_buffer
# | clang_rt.profile-x86_64.lib(InstrProfilingWriter.c.obj) : error LNK2001: unresolved external symbol __llvm_profile_end_vtables
```
>From 1e24693028453486a9b62199226d299c49ca299a Mon Sep 17 00:00:00 2001
From: mingmingl <mingmingl at google.com>
Date: Wed, 21 Feb 2024 21:36:49 -0800
Subject: [PATCH] revert type profiling change as it breaks compiler-rt test on
non-Linux platforms
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 20 ++++++++-----------
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 12 +++++++----
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 75be97ff32bbe5..f7275eb7c77bb3 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3240,8 +3240,7 @@ static std::optional<uint64_t> getExactInteger(const APFloat &APF,
// Note that this method will also match potentially unappealing index
// sequences, like <i32 0, i32 50939494>, however it is left to the caller to
// determine whether this is worth generating code for.
-static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op,
- unsigned EltSizeInBits) {
+static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op) {
unsigned NumElts = Op.getNumOperands();
assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unexpected BUILD_VECTOR");
bool IsInteger = Op.getValueType().isInteger();
@@ -3249,7 +3248,7 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op,
std::optional<unsigned> SeqStepDenom;
std::optional<int64_t> SeqStepNum, SeqAddend;
std::optional<std::pair<uint64_t, unsigned>> PrevElt;
- assert(EltSizeInBits >= Op.getValueType().getScalarSizeInBits());
+ unsigned EltSizeInBits = Op.getValueType().getScalarSizeInBits();
for (unsigned Idx = 0; Idx < NumElts; Idx++) {
// Assume undef elements match the sequence; we just have to be careful
// when interpolating across them.
@@ -3262,14 +3261,14 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op,
if (!isa<ConstantSDNode>(Op.getOperand(Idx)))
return std::nullopt;
Val = Op.getConstantOperandVal(Idx) &
- maskTrailingOnes<uint64_t>(Op.getScalarValueSizeInBits());
+ maskTrailingOnes<uint64_t>(EltSizeInBits);
} else {
// The BUILD_VECTOR must be all constants.
if (!isa<ConstantFPSDNode>(Op.getOperand(Idx)))
return std::nullopt;
if (auto ExactInteger = getExactInteger(
cast<ConstantFPSDNode>(Op.getOperand(Idx))->getValueAPF(),
- Op.getScalarValueSizeInBits()))
+ EltSizeInBits))
Val = *ExactInteger;
else
return std::nullopt;
@@ -3325,11 +3324,11 @@ static std::optional<VIDSequence> isSimpleVIDSequence(SDValue Op,
uint64_t Val;
if (IsInteger) {
Val = Op.getConstantOperandVal(Idx) &
- maskTrailingOnes<uint64_t>(Op.getScalarValueSizeInBits());
+ maskTrailingOnes<uint64_t>(EltSizeInBits);
} else {
Val = *getExactInteger(
cast<ConstantFPSDNode>(Op.getOperand(Idx))->getValueAPF(),
- Op.getScalarValueSizeInBits());
+ EltSizeInBits);
}
uint64_t ExpectedVal =
(int64_t)(Idx * (uint64_t)*SeqStepNum) / *SeqStepDenom;
@@ -3599,7 +3598,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
// Try and match index sequences, which we can lower to the vid instruction
// with optional modifications. An all-undef vector is matched by
// getSplatValue, above.
- if (auto SimpleVID = isSimpleVIDSequence(Op, Op.getScalarValueSizeInBits())) {
+ if (auto SimpleVID = isSimpleVIDSequence(Op)) {
int64_t StepNumerator = SimpleVID->StepNumerator;
unsigned StepDenominator = SimpleVID->StepDenominator;
int64_t Addend = SimpleVID->Addend;
@@ -15979,10 +15978,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
if (Index.getOpcode() == ISD::BUILD_VECTOR &&
MGN->getExtensionType() == ISD::NON_EXTLOAD && isTypeLegal(VT)) {
- // The sequence will be XLenVT, not the type of Index. Tell
- // isSimpleVIDSequence this so we avoid overflow.
- if (std::optional<VIDSequence> SimpleVID =
- isSimpleVIDSequence(Index, Subtarget.getXLen());
+ if (std::optional<VIDSequence> SimpleVID = isSimpleVIDSequence(Index);
SimpleVID && SimpleVID->StepDenominator == 1) {
const int64_t StepNumerator = SimpleVID->StepNumerator;
const int64_t Addend = SimpleVID->Addend;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index 88c299a19fb4e8..60eec356773bfa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -15086,19 +15086,23 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
ret <32 x i64> %x
}
+; FIXME: This is a miscompile triggered by the mgather ->
+; riscv.masked.strided.load combine. In order for it to trigger we need either a
+; strided gather that RISCVGatherScatterLowering doesn't pick up, or a new
+; strided gather generated by the widening sew combine.
define <4 x i32> @masked_gather_widen_sew_negative_stride(ptr %base) {
; RV32V-LABEL: masked_gather_widen_sew_negative_stride:
; RV32V: # %bb.0:
-; RV32V-NEXT: addi a0, a0, 136
-; RV32V-NEXT: li a1, -136
+; RV32V-NEXT: addi a0, a0, -120
+; RV32V-NEXT: li a1, 120
; RV32V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32V-NEXT: vlse64.v v8, (a0), a1
; RV32V-NEXT: ret
;
; RV64V-LABEL: masked_gather_widen_sew_negative_stride:
; RV64V: # %bb.0:
-; RV64V-NEXT: addi a0, a0, 136
-; RV64V-NEXT: li a1, -136
+; RV64V-NEXT: addi a0, a0, -120
+; RV64V-NEXT: li a1, 120
; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64V-NEXT: vlse64.v v8, (a0), a1
; RV64V-NEXT: ret
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