[llvm] [RISCV] Vector sub (zext, zext) -> sext (sub (zext, zext)) (PR #82455)

[Philip Reames via llvm-commits]

================
@@ -12846,21 +12846,43 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineSubOfBoolean(N, DAG))
     return V;
 
+  EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   // fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
   if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
       isNullConstant(N1.getOperand(1))) {
     ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
     if (CCVal == ISD::SETLT) {
-      EVT VT = N->getValueType(0);
       SDLoc DL(N);
       unsigned ShAmt = N0.getValueSizeInBits() - 1;
       return DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0),
                          DAG.getConstant(ShAmt, DL, VT));
     }
   }
 
+  // sub (zext, zext) -> sext (sub (zext, zext))
+  //   where the sum of the extend widths match, and the inner zexts
+  //   add at least one bit.  (For profitability on rvv, we use a
+  //   power of two for both inner and outer extend.)
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preames wrote:

This is a case of a comment being out of sync with my mental model.  Will fix, but let me explain what I'm thinking and you can tell me if this is sane or not.

I was originally intending to have a isTypeLegal check on both VT and SrcVT.  That combined with the srcvt > 8 check should ensure that all of the types are e8, e16, e32, or e64.

Then I started thinking about illegal types.  I think they fall into two camps - reasonable ones such as i128, and odd ones such as i34.  For the former, narrowing before legalization (splitting, I think?) seems likely profitable.  For the later, we might end up with an e.g. e17 intermediate type, but that'll get promoted to i32 and i64 respectively.  So, reasonable overall result?  (Though, I now notice there's an edge case here with e.g. i33 not having a half sized type.)

What do you think, should I fix the edge case and allow illegal types?  Require legal types?  Something else?


https://github.com/llvm/llvm-project/pull/82455