[llvm] [RISCV] Use PromoteSetCCOperands to promote operands for UMAX/UMIN during type legalization. (PR #82716)

[Craig Topper via llvm-commits]

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@@ -1343,10 +1343,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+
   // It doesn't matter if we sign extend or zero extend in the inputs. So do
-  // whatever is best for the target.
-  SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
-  SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
+  // whatever is best for the target and the promoted operands. We can reuse
+  // PromoteSetCCOperands by passing it an unsigned predicate.
+  PromoteSetCCOperands(LHS, RHS, ISD::SETUGT);
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topperc wrote:

I've separated the core part of PromoteSetCCOperands into a helper that is independent of the condition code.

I think this could also be used for USUBSAT and maybe other places so distancing from SETCC seemed like a good idea.

https://github.com/llvm/llvm-project/pull/82716