[llvm] [PowerPC] Do not generate `isel` instruction if target doesn't have this instruction (PR #72845)

[Chen Zheng via llvm-commits]

chenzheng1030 wrote:

If I understand correctly, selecting `isel/isel8` to branch instructions if `hasISEL()` == false in the ISEL phase instead of the late expand-isel pass can make the sink related pass sink the true/false value to the related branch.
Like the case [llvm/test/CodeGen/PowerPC/expand-isel-to-branch.ll](https://github.com/llvm/llvm-project/pull/72845/files#diff-8550e7b1ad6ad4554dca6b96b772f29cd2f6d7d3da509dbe79554e1474fef8fa) showed:
Before the patch:
```
;  CHECK-NEXT:    addi 5, 4, 1 // value in true branch, post-dominate the entry block
; CHECK-NEXT:    li 4, 1 // value in the false branch,  post-dominate the entry block
; CHECK-NEXT:    bc 12, 0, L..BB0_1
; CHECK-NEXT:    b L..BB0_2
; CHECK-NEXT:  L..BB0_1: # %bb
; CHECK-NEXT:    addi 4, 5, 0
; CHECK-NEXT:  L..BB0_2: # %bb
; CHECK-NEXT:    stw 4, 0(3)
```

after the patch:
```
; CHECK-NEXT:    blt 0, L..BB0_2
; CHECK-NEXT:  # %bb.1: # %bb
; CHECK-NEXT:    li 4, 1   // value in the false branch, don't post-dominate the entry block
; CHECK-NEXT:    b L..BB0_3
; CHECK-NEXT:  L..BB0_2:
; CHECK-NEXT:    addi 4, 4, 1 // value in the true branch, don't post-dominate the entry block
; CHECK-NEXT:  L..BB0_3: # %bb
; CHECK-NEXT:    stw 4, 0(3)
```

I think this advantage should be applied to float select instructions and vector selection instructions too? The issue is for float select instructions and vector selection instructions, there is no option to disable them. So it is not an issue that needs to be addressed here.

Since now the SELECT are selected in the DAG ISel pass with the guard `hasISEL()`, is it necessary to keep pass expand-isel which also depends on `hasISEL()` in the ppc backend?  And it would be good to have a perf test.

https://github.com/llvm/llvm-project/pull/72845