[llvm] clarify semantics of masked vector load/store (PR #82469)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-ir

Author: Ralf Jung (RalfJung)

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<summary>Changes</summary>

This is based on what I think has to follow from the statement about preventing exceptions. But I don't actually know what LLVM IR passes will do with these intrinsics, so this requires careful review by someone who does. :)

@<!-- -->nikic do you know these passes / know who knows these passes to do the review?

Also, there's an open question that remains: for the purpose of `noalias`, do these operations access the masked-off lanes or not? I sure hope they don't, but I realized that while data races are mentioned, `noalias` is not.

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Full diff: https://github.com/llvm/llvm-project/pull/82469.diff


1 Files Affected:

- (modified) llvm/docs/LangRef.rst (+2) 


``````````diff
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index fd2e3aacd0169c..496773c4d3d386 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -23752,6 +23752,7 @@ Semantics:
 
 The '``llvm.masked.load``' intrinsic is designed for conditional reading of selected vector elements in a single IR operation. It is useful for targets that support vector masked loads and allows vectorizing predicated basic blocks on these targets. Other targets may support this intrinsic differently, for example by lowering it into a sequence of branches that guard scalar load operations.
 The result of this operation is equivalent to a regular vector load instruction followed by a 'select' between the loaded and the passthru values, predicated on the same mask. However, using this intrinsic prevents exceptions on memory access to masked-off lanes.
+In particular, this means that only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation).
 
 
 ::
@@ -23794,6 +23795,7 @@ Semantics:
 
 The '``llvm.masked.store``' intrinsics is designed for conditional writing of selected vector elements in a single IR operation. It is useful for targets that support vector masked store and allows vectorizing predicated basic blocks on these targets. Other targets may support this intrinsic differently, for example by lowering it into a sequence of branches that guard scalar store operations.
 The result of this operation is equivalent to a load-modify-store sequence. However, using this intrinsic prevents exceptions and data races on memory access to masked-off lanes.
+In particular, this means that only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation).
 
 ::
 

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https://github.com/llvm/llvm-project/pull/82469