[llvm] [RISCV] Teach RISCVMakeCompressible handle Zca/Zcf/Zce/Zcd. (PR #81844)
Yeting Kuo via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 21 22:53:30 PST 2024
https://github.com/yetingk updated https://github.com/llvm/llvm-project/pull/81844
>From ccb94a9ff3032eedd6a1ab9862cb72e4583f8d65 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Thu, 15 Feb 2024 00:39:13 -0800
Subject: [PATCH 1/3] [RISCV] Teach RISCVMakeCompressible handle
Zca/Zcf/Zce/Zcd.
Make targets which don't have C but have Zca/Zcf/Zce/Zcd benefit from this pass.
---
.../Target/RISCV/RISCVMakeCompressible.cpp | 31 ++++++++++++++-----
llvm/lib/Target/RISCV/RISCVSubtarget.h | 4 +++
llvm/test/CodeGen/RISCV/make-compressible.mir | 4 +++
3 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index ff21fe1d406463..6759be63d46bab 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -143,19 +143,35 @@ static bool isCompressedReg(Register Reg) {
// Return true if MI is a load for which there exists a compressed version.
static bool isCompressibleLoad(const MachineInstr &MI) {
const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>();
- const unsigned Opcode = MI.getOpcode();
- return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) ||
- Opcode == RISCV::LD || Opcode == RISCV::FLD;
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case RISCV::LW:
+ case RISCV::LD:
+ return STI.hasStdExtCOrZca();
+ case RISCV::FLW:
+ return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
+ case RISCV::FLD:
+ return STI.hasStdExtCOrZcd();
+ }
}
// Return true if MI is a store for which there exists a compressed version.
static bool isCompressibleStore(const MachineInstr &MI) {
const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>();
- const unsigned Opcode = MI.getOpcode();
- return Opcode == RISCV::SW || (!STI.is64Bit() && Opcode == RISCV::FSW) ||
- Opcode == RISCV::SD || Opcode == RISCV::FSD;
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case RISCV::SW:
+ case RISCV::SD:
+ return STI.hasStdExtCOrZca();
+ case RISCV::FSW:
+ return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
+ case RISCV::FSD:
+ return STI.hasStdExtCOrZcd();
+ }
}
// Find a single register and/or large offset which, if compressible, would
@@ -324,8 +340,7 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
const RISCVInstrInfo &TII = *STI.getInstrInfo();
// This optimization only makes sense if compressed instructions are emitted.
- // FIXME: Support Zca, Zcf, Zcd granularity.
- if (!STI.hasStdExtC())
+ if (!STI.hasStdExtZca() && !STI.hasStdExtCOrZcfOrZce() && !STI.hasStdExtZcd())
return false;
for (MachineBasicBlock &MBB : Fn) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 8c55efa69a6a5f..d23b0c684fdc23 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -143,6 +143,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
#include "RISCVGenSubtargetInfo.inc"
bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
+ bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
+ bool hasStdExtCOrZcfOrZce() const {
+ return HasStdExtC || HasStdExtZcf || HasStdExtZce;
+ }
bool hasStdExtZvl() const { return ZvlLen != 0; }
bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
diff --git a/llvm/test/CodeGen/RISCV/make-compressible.mir b/llvm/test/CodeGen/RISCV/make-compressible.mir
index 2105a13bc8c7b7..d718a21fa5d9e8 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible.mir
@@ -3,6 +3,10 @@
# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV32 %s
# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+f,+d -simplify-mir \
# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV64 %s
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zca,+zcf,+zcd -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV32 %s
+# RUN: llc -o - %s -mtriple=riscv64 -mattr=+zca,+zcd -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV64 %s
--- |
define void @store_common_value(ptr %a, ptr %b, ptr %c) #0 {
>From ee43be959d42c00b97f067b31a157b8637972995 Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Thu, 15 Feb 2024 19:22:51 -0800
Subject: [PATCH 2/3] Add test cases for zca and zcf.
---
llvm/test/CodeGen/RISCV/make-compressible.mir | 503 +++++++++++++-----
1 file changed, 373 insertions(+), 130 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/make-compressible.mir b/llvm/test/CodeGen/RISCV/make-compressible.mir
index d718a21fa5d9e8..03da38a6863e71 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible.mir
@@ -1,12 +1,14 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+f,+d -simplify-mir \
-# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV32 %s
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32C %s
# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+f,+d -simplify-mir \
-# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV64 %s
-# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zca,+zcf,+zcd -simplify-mir \
-# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV32 %s
-# RUN: llc -o - %s -mtriple=riscv64 -mattr=+zca,+zcd -simplify-mir \
-# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefix=RV64 %s
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV64,RV64C %s
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+d,+zcf -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32ZCF %s
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+d,+zca -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32ZCA %s
+# RUN: llc -o - %s -mtriple=riscv64 -mattr=+d,+zca -simplify-mir \
+# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV64,RV64ZCA %s
--- |
define void @store_common_value(ptr %a, ptr %b, ptr %c) #0 {
@@ -292,7 +294,7 @@
ret { double, double } %3
}
- attributes #0 = { minsize "target-features"="+c,+f,+d" }
+ attributes #0 = { minsize }
...
---
@@ -310,6 +312,7 @@ body: |
; RV32-NEXT: SW $x13, killed renamable $x11, 0 :: (store (s32) into %ir.b)
; RV32-NEXT: SW $x13, killed renamable $x12, 0 :: (store (s32) into %ir.c)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_value
; RV64: liveins: $x10, $x11, $x12
; RV64-NEXT: {{ $}}
@@ -331,14 +334,15 @@ body: |
bb.0.entry:
liveins: $x10, $x11, $x12, $f16_f
- ; RV32-LABEL: name: store_common_value_float
- ; RV32: liveins: $x10, $x11, $x12, $f16_f
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $f15_f = FSGNJ_S $f16_f, $f16_f
- ; RV32-NEXT: FSW $f15_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
- ; RV32-NEXT: FSW $f15_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
- ; RV32-NEXT: FSW killed $f15_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
- ; RV32-NEXT: PseudoRET
+ ; RV32C-LABEL: name: store_common_value_float
+ ; RV32C: liveins: $x10, $x11, $x12, $f16_f
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $f15_f = FSGNJ_S $f16_f, $f16_f
+ ; RV32C-NEXT: FSW $f15_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
+ ; RV32C-NEXT: FSW $f15_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
+ ; RV32C-NEXT: FSW killed $f15_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
+ ; RV32C-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_value_float
; RV64: liveins: $x10, $x11, $x12, $f16_f
; RV64-NEXT: {{ $}}
@@ -346,6 +350,23 @@ body: |
; RV64-NEXT: FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
; RV64-NEXT: FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
; RV64-NEXT: PseudoRET
+ ;
+ ; RV32ZCF-LABEL: name: store_common_value_float
+ ; RV32ZCF: liveins: $x10, $x11, $x12, $f16_f
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: $f15_f = FSGNJ_S $f16_f, $f16_f
+ ; RV32ZCF-NEXT: FSW $f15_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
+ ; RV32ZCF-NEXT: FSW $f15_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
+ ; RV32ZCF-NEXT: FSW killed $f15_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
+ ; RV32ZCF-NEXT: PseudoRET
+ ;
+ ; RV32ZCA-LABEL: name: store_common_value_float
+ ; RV32ZCA: liveins: $x10, $x11, $x12, $f16_f
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
+ ; RV32ZCA-NEXT: FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
+ ; RV32ZCA-NEXT: FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
+ ; RV32ZCA-NEXT: PseudoRET
FSW renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
FSW renamable $f16_f, killed renamable $x11, 0 :: (store (s32) into %ir.b)
FSW killed renamable $f16_f, killed renamable $x12, 0 :: (store (s32) into %ir.c)
@@ -359,22 +380,47 @@ body: |
bb.0.entry:
liveins: $x10, $x11, $x12, $f16_d
- ; RV32-LABEL: name: store_common_value_double
- ; RV32: liveins: $x10, $x11, $x12, $f16_d
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $f15_d = FSGNJ_D $f16_d, $f16_d
- ; RV32-NEXT: FSD $f15_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
- ; RV32-NEXT: FSD $f15_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
- ; RV32-NEXT: FSD killed $f15_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
- ; RV32-NEXT: PseudoRET
- ; RV64-LABEL: name: store_common_value_double
- ; RV64: liveins: $x10, $x11, $x12, $f16_d
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: $f15_d = FSGNJ_D $f16_d, $f16_d
- ; RV64-NEXT: FSD $f15_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
- ; RV64-NEXT: FSD $f15_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
- ; RV64-NEXT: FSD killed $f15_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
- ; RV64-NEXT: PseudoRET
+ ; RV32C-LABEL: name: store_common_value_double
+ ; RV32C: liveins: $x10, $x11, $x12, $f16_d
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $f15_d = FSGNJ_D $f16_d, $f16_d
+ ; RV32C-NEXT: FSD $f15_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV32C-NEXT: FSD $f15_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ ; RV32C-NEXT: FSD killed $f15_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ ; RV32C-NEXT: PseudoRET
+ ;
+ ; RV64C-LABEL: name: store_common_value_double
+ ; RV64C: liveins: $x10, $x11, $x12, $f16_d
+ ; RV64C-NEXT: {{ $}}
+ ; RV64C-NEXT: $f15_d = FSGNJ_D $f16_d, $f16_d
+ ; RV64C-NEXT: FSD $f15_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV64C-NEXT: FSD $f15_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ ; RV64C-NEXT: FSD killed $f15_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ ; RV64C-NEXT: PseudoRET
+ ;
+ ; RV32ZCF-LABEL: name: store_common_value_double
+ ; RV32ZCF: liveins: $x10, $x11, $x12, $f16_d
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV32ZCF-NEXT: FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ ; RV32ZCF-NEXT: FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ ; RV32ZCF-NEXT: PseudoRET
+ ;
+ ; RV32ZCA-LABEL: name: store_common_value_double
+ ; RV32ZCA: liveins: $x10, $x11, $x12, $f16_d
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV32ZCA-NEXT: FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ ; RV32ZCA-NEXT: FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ ; RV32ZCA-NEXT: PseudoRET
+ ;
+ ; RV64ZCA-LABEL: name: store_common_value_double
+ ; RV64ZCA: liveins: $x10, $x11, $x12, $f16_d
+ ; RV64ZCA-NEXT: {{ $}}
+ ; RV64ZCA-NEXT: FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
+ ; RV64ZCA-NEXT: FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
+ ; RV64ZCA-NEXT: FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
+ ; RV64ZCA-NEXT: PseudoRET
FSD renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
FSD renamable $f16_d, killed renamable $x11, 0 :: (store (s64) into %ir.b)
FSD killed renamable $f16_d, killed renamable $x12, 0 :: (store (s64) into %ir.c)
@@ -399,6 +445,7 @@ body: |
; RV32-NEXT: renamable $x10 = ADDI $x0, 5
; RV32-NEXT: SW killed renamable $x10, killed $x11, 0 :: (volatile store (s32) into %ir.p)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_ptr
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -436,6 +483,7 @@ body: |
; RV32-NEXT: SW killed renamable $x10, $x11, 0 :: (volatile store (s32) into %ir.p)
; RV32-NEXT: SW killed $x11, $x11, 0 :: (volatile store (s32) into %ir.q)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_ptr_self
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -461,14 +509,15 @@ body: |
bb.0.entry:
liveins: $x16, $f10_f, $f11_f, $f12_f
- ; RV32-LABEL: name: store_common_ptr_float
- ; RV32: liveins: $x16, $f10_f, $f11_f, $f12_f
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x10 = ADDI $x16, 0
- ; RV32-NEXT: FSW killed renamable $f10_f, $x10, 0 :: (volatile store (s32) into %ir.p)
- ; RV32-NEXT: FSW killed renamable $f11_f, $x10, 0 :: (volatile store (s32) into %ir.p)
- ; RV32-NEXT: FSW killed renamable $f12_f, killed $x10, 0 :: (volatile store (s32) into %ir.p)
- ; RV32-NEXT: PseudoRET
+ ; RV32C-LABEL: name: store_common_ptr_float
+ ; RV32C: liveins: $x16, $f10_f, $f11_f, $f12_f
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x10 = ADDI $x16, 0
+ ; RV32C-NEXT: FSW killed renamable $f10_f, $x10, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32C-NEXT: FSW killed renamable $f11_f, $x10, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32C-NEXT: FSW killed renamable $f12_f, killed $x10, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32C-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_ptr_float
; RV64: liveins: $x16, $f10_f, $f11_f, $f12_f
; RV64-NEXT: {{ $}}
@@ -476,6 +525,23 @@ body: |
; RV64-NEXT: FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
; RV64-NEXT: FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
; RV64-NEXT: PseudoRET
+ ;
+ ; RV32ZCF-LABEL: name: store_common_ptr_float
+ ; RV32ZCF: liveins: $x16, $f10_f, $f11_f, $f12_f
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: $x10 = ADDI $x16, 0
+ ; RV32ZCF-NEXT: FSW killed renamable $f10_f, $x10, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32ZCF-NEXT: FSW killed renamable $f11_f, $x10, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32ZCF-NEXT: FSW killed renamable $f12_f, killed $x10, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32ZCF-NEXT: PseudoRET
+ ;
+ ; RV32ZCA-LABEL: name: store_common_ptr_float
+ ; RV32ZCA: liveins: $x16, $f10_f, $f11_f, $f12_f
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32ZCA-NEXT: FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32ZCA-NEXT: FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
+ ; RV32ZCA-NEXT: PseudoRET
FSW killed renamable $f10_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
FSW killed renamable $f11_f, renamable $x16, 0 :: (volatile store (s32) into %ir.p)
FSW killed renamable $f12_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
@@ -489,22 +555,47 @@ body: |
bb.0.entry:
liveins: $x16, $f10_d, $f11_d, $f12_d
- ; RV32-LABEL: name: store_common_ptr_double
- ; RV32: liveins: $x16, $f10_d, $f11_d, $f12_d
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x10 = ADDI $x16, 0
- ; RV32-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p)
- ; RV32-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p)
- ; RV32-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p)
- ; RV32-NEXT: PseudoRET
- ; RV64-LABEL: name: store_common_ptr_double
- ; RV64: liveins: $x16, $f10_d, $f11_d, $f12_d
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: $x10 = ADDI $x16, 0
- ; RV64-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p)
- ; RV64-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p)
- ; RV64-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p)
- ; RV64-NEXT: PseudoRET
+ ; RV32C-LABEL: name: store_common_ptr_double
+ ; RV32C: liveins: $x16, $f10_d, $f11_d, $f12_d
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x10 = ADDI $x16, 0
+ ; RV32C-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32C-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32C-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32C-NEXT: PseudoRET
+ ;
+ ; RV64C-LABEL: name: store_common_ptr_double
+ ; RV64C: liveins: $x16, $f10_d, $f11_d, $f12_d
+ ; RV64C-NEXT: {{ $}}
+ ; RV64C-NEXT: $x10 = ADDI $x16, 0
+ ; RV64C-NEXT: FSD killed renamable $f10_d, $x10, 0 :: (volatile store (s64) into %ir.p)
+ ; RV64C-NEXT: FSD killed renamable $f11_d, $x10, 0 :: (volatile store (s64) into %ir.p)
+ ; RV64C-NEXT: FSD killed renamable $f12_d, killed $x10, 0 :: (volatile store (s64) into %ir.p)
+ ; RV64C-NEXT: PseudoRET
+ ;
+ ; RV32ZCF-LABEL: name: store_common_ptr_double
+ ; RV32ZCF: liveins: $x16, $f10_d, $f11_d, $f12_d
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32ZCF-NEXT: FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32ZCF-NEXT: FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32ZCF-NEXT: PseudoRET
+ ;
+ ; RV32ZCA-LABEL: name: store_common_ptr_double
+ ; RV32ZCA: liveins: $x16, $f10_d, $f11_d, $f12_d
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32ZCA-NEXT: FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32ZCA-NEXT: FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV32ZCA-NEXT: PseudoRET
+ ;
+ ; RV64ZCA-LABEL: name: store_common_ptr_double
+ ; RV64ZCA: liveins: $x16, $f10_d, $f11_d, $f12_d
+ ; RV64ZCA-NEXT: {{ $}}
+ ; RV64ZCA-NEXT: FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV64ZCA-NEXT: FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV64ZCA-NEXT: FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
+ ; RV64ZCA-NEXT: PseudoRET
FSD killed renamable $f10_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
FSD killed renamable $f11_d, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
FSD killed renamable $f12_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
@@ -526,6 +617,7 @@ body: |
; RV32-NEXT: dead renamable $x10 = LW $x11, 0 :: (volatile load (s32) from %ir.p)
; RV32-NEXT: dead renamable $x10 = LW killed $x11, 0 :: (volatile load (s32) from %ir.p)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: load_common_ptr
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -547,14 +639,15 @@ body: |
bb.0.entry:
liveins: $x16
- ; RV32-LABEL: name: load_common_ptr_float
- ; RV32: liveins: $x16
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x10 = ADDI $x16, 0
- ; RV32-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g)
- ; RV32-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1)
- ; RV32-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2)
- ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ; RV32C-LABEL: name: load_common_ptr_float
+ ; RV32C: liveins: $x16
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x10 = ADDI $x16, 0
+ ; RV32C-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g)
+ ; RV32C-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1)
+ ; RV32C-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2)
+ ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ;
; RV64-LABEL: name: load_common_ptr_float
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -562,6 +655,23 @@ body: |
; RV64-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
; RV64-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ;
+ ; RV32ZCF-LABEL: name: load_common_ptr_float
+ ; RV32ZCF: liveins: $x16
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: $x10 = ADDI $x16, 0
+ ; RV32ZCF-NEXT: renamable $f10_f = FLW $x10, 0 :: (load (s32) from %ir.g)
+ ; RV32ZCF-NEXT: renamable $f11_f = FLW $x10, 4 :: (load (s32) from %ir.arrayidx1)
+ ; RV32ZCF-NEXT: renamable $f12_f = FLW killed $x10, 8 :: (load (s32) from %ir.arrayidx2)
+ ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ;
+ ; RV32ZCA-LABEL: name: load_common_ptr_float
+ ; RV32ZCA: liveins: $x16
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
+ ; RV32ZCA-NEXT: renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
+ ; RV32ZCA-NEXT: renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
+ ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
renamable $f10_f = FLW renamable $x16, 0 :: (load (s32) from %ir.g)
renamable $f11_f = FLW renamable $x16, 4 :: (load (s32) from %ir.arrayidx1)
renamable $f12_f = FLW killed renamable $x16, 8 :: (load (s32) from %ir.arrayidx2)
@@ -575,22 +685,47 @@ body: |
bb.0.entry:
liveins: $x16
- ; RV32-LABEL: name: load_common_ptr_double
- ; RV32: liveins: $x16
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x10 = ADDI $x16, 0
- ; RV32-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
- ; RV32-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
- ; RV32-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
- ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
- ; RV64-LABEL: name: load_common_ptr_double
- ; RV64: liveins: $x16
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: $x10 = ADDI $x16, 0
- ; RV64-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
- ; RV64-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
- ; RV64-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
- ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ; RV32C-LABEL: name: load_common_ptr_double
+ ; RV32C: liveins: $x16
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x10 = ADDI $x16, 0
+ ; RV32C-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
+ ; RV32C-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
+ ; RV32C-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
+ ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV64C-LABEL: name: load_common_ptr_double
+ ; RV64C: liveins: $x16
+ ; RV64C-NEXT: {{ $}}
+ ; RV64C-NEXT: $x10 = ADDI $x16, 0
+ ; RV64C-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
+ ; RV64C-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
+ ; RV64C-NEXT: renamable $f12_d = FLD killed $x10, 16 :: (load (s64) from %ir.arrayidx2)
+ ; RV64C-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV32ZCF-LABEL: name: load_common_ptr_double
+ ; RV32ZCF: liveins: $x16
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
+ ; RV32ZCF-NEXT: renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
+ ; RV32ZCF-NEXT: renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2)
+ ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV32ZCA-LABEL: name: load_common_ptr_double
+ ; RV32ZCA: liveins: $x16
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
+ ; RV32ZCA-NEXT: renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
+ ; RV32ZCA-NEXT: renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2)
+ ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV64ZCA-LABEL: name: load_common_ptr_double
+ ; RV64ZCA: liveins: $x16
+ ; RV64ZCA-NEXT: {{ $}}
+ ; RV64ZCA-NEXT: renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
+ ; RV64ZCA-NEXT: renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
+ ; RV64ZCA-NEXT: renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2)
+ ; RV64ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
renamable $f12_d = FLD killed renamable $x16, 16 :: (load (s64) from %ir.arrayidx2)
@@ -617,6 +752,7 @@ body: |
; RV32-NEXT: renamable $x11 = ADDI $x0, 7
; RV32-NEXT: SW killed renamable $x11, killed $x12, 28 :: (volatile store (s32) into %ir.3)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_large_offset
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -648,15 +784,16 @@ body: |
bb.0.entry:
liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
- ; RV32-LABEL: name: store_large_offset_float
- ; RV32: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x11 = ADDI $x10, 384
- ; RV32-NEXT: FSW killed renamable $f10_f, $x11, 16 :: (volatile store (s32) into %ir.0)
- ; RV32-NEXT: FSW killed renamable $f11_f, $x11, 20 :: (volatile store (s32) into %ir.1)
- ; RV32-NEXT: FSW killed renamable $f12_f, $x11, 24 :: (volatile store (s32) into %ir.2)
- ; RV32-NEXT: FSW killed renamable $f13_f, killed $x11, 28 :: (volatile store (s32) into %ir.3)
- ; RV32-NEXT: PseudoRET
+ ; RV32C-LABEL: name: store_large_offset_float
+ ; RV32C: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x11 = ADDI $x10, 384
+ ; RV32C-NEXT: FSW killed renamable $f10_f, $x11, 16 :: (volatile store (s32) into %ir.0)
+ ; RV32C-NEXT: FSW killed renamable $f11_f, $x11, 20 :: (volatile store (s32) into %ir.1)
+ ; RV32C-NEXT: FSW killed renamable $f12_f, $x11, 24 :: (volatile store (s32) into %ir.2)
+ ; RV32C-NEXT: FSW killed renamable $f13_f, killed $x11, 28 :: (volatile store (s32) into %ir.3)
+ ; RV32C-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_large_offset_float
; RV64: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
; RV64-NEXT: {{ $}}
@@ -665,6 +802,25 @@ body: |
; RV64-NEXT: FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
; RV64-NEXT: FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3)
; RV64-NEXT: PseudoRET
+ ;
+ ; RV32ZCF-LABEL: name: store_large_offset_float
+ ; RV32ZCF: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: $x11 = ADDI $x10, 384
+ ; RV32ZCF-NEXT: FSW killed renamable $f10_f, $x11, 16 :: (volatile store (s32) into %ir.0)
+ ; RV32ZCF-NEXT: FSW killed renamable $f11_f, $x11, 20 :: (volatile store (s32) into %ir.1)
+ ; RV32ZCF-NEXT: FSW killed renamable $f12_f, $x11, 24 :: (volatile store (s32) into %ir.2)
+ ; RV32ZCF-NEXT: FSW killed renamable $f13_f, killed $x11, 28 :: (volatile store (s32) into %ir.3)
+ ; RV32ZCF-NEXT: PseudoRET
+ ;
+ ; RV32ZCA-LABEL: name: store_large_offset_float
+ ; RV32ZCA: liveins: $x10, $f10_f, $f11_f, $f12_f, $f13_f
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
+ ; RV32ZCA-NEXT: FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1)
+ ; RV32ZCA-NEXT: FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
+ ; RV32ZCA-NEXT: FSW killed renamable $f13_f, killed renamable $x10, 412 :: (volatile store (s32) into %ir.3)
+ ; RV32ZCA-NEXT: PseudoRET
FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
FSW killed renamable $f11_f, renamable $x10, 404 :: (volatile store (s32) into %ir.1)
FSW killed renamable $f12_f, renamable $x10, 408 :: (volatile store (s32) into %ir.2)
@@ -679,24 +835,52 @@ body: |
bb.0.entry:
liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
- ; RV32-LABEL: name: store_large_offset_double
- ; RV32: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x11 = ADDI $x10, 768
- ; RV32-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0)
- ; RV32-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1)
- ; RV32-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2)
- ; RV32-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3)
- ; RV32-NEXT: PseudoRET
- ; RV64-LABEL: name: store_large_offset_double
- ; RV64: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: $x11 = ADDI $x10, 768
- ; RV64-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0)
- ; RV64-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1)
- ; RV64-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2)
- ; RV64-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3)
- ; RV64-NEXT: PseudoRET
+ ; RV32C-LABEL: name: store_large_offset_double
+ ; RV32C: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x11 = ADDI $x10, 768
+ ; RV32C-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0)
+ ; RV32C-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1)
+ ; RV32C-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2)
+ ; RV32C-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3)
+ ; RV32C-NEXT: PseudoRET
+ ;
+ ; RV64C-LABEL: name: store_large_offset_double
+ ; RV64C: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
+ ; RV64C-NEXT: {{ $}}
+ ; RV64C-NEXT: $x11 = ADDI $x10, 768
+ ; RV64C-NEXT: FSD killed renamable $f10_d, $x11, 32 :: (volatile store (s64) into %ir.0)
+ ; RV64C-NEXT: FSD killed renamable $f11_d, $x11, 40 :: (volatile store (s64) into %ir.1)
+ ; RV64C-NEXT: FSD killed renamable $f12_d, $x11, 48 :: (volatile store (s64) into %ir.2)
+ ; RV64C-NEXT: FSD killed renamable $f13_d, killed $x11, 56 :: (volatile store (s64) into %ir.3)
+ ; RV64C-NEXT: PseudoRET
+ ;
+ ; RV32ZCF-LABEL: name: store_large_offset_double
+ ; RV32ZCF: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
+ ; RV32ZCF-NEXT: FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
+ ; RV32ZCF-NEXT: FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2)
+ ; RV32ZCF-NEXT: FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3)
+ ; RV32ZCF-NEXT: PseudoRET
+ ;
+ ; RV32ZCA-LABEL: name: store_large_offset_double
+ ; RV32ZCA: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
+ ; RV32ZCA-NEXT: FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
+ ; RV32ZCA-NEXT: FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2)
+ ; RV32ZCA-NEXT: FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3)
+ ; RV32ZCA-NEXT: PseudoRET
+ ;
+ ; RV64ZCA-LABEL: name: store_large_offset_double
+ ; RV64ZCA: liveins: $x10, $f10_d, $f11_d, $f12_d, $f13_d
+ ; RV64ZCA-NEXT: {{ $}}
+ ; RV64ZCA-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
+ ; RV64ZCA-NEXT: FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
+ ; RV64ZCA-NEXT: FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2)
+ ; RV64ZCA-NEXT: FSD killed renamable $f13_d, killed renamable $x10, 824 :: (volatile store (s64) into %ir.3)
+ ; RV64ZCA-NEXT: PseudoRET
FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
FSD killed renamable $f11_d, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
FSD killed renamable $f12_d, renamable $x10, 816 :: (volatile store (s64) into %ir.2)
@@ -720,6 +904,7 @@ body: |
; RV32-NEXT: dead renamable $x11 = LW $x12, 24 :: (volatile load (s32) from %ir.2)
; RV32-NEXT: dead renamable $x10 = LW killed $x12, 28 :: (volatile load (s32) from %ir.3)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: load_large_offset
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -743,14 +928,15 @@ body: |
bb.0.entry:
liveins: $x10
- ; RV32-LABEL: name: load_large_offset_float
- ; RV32: liveins: $x10
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x11 = ADDI $x10, 384
- ; RV32-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx)
- ; RV32-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1)
- ; RV32-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2)
- ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ; RV32C-LABEL: name: load_large_offset_float
+ ; RV32C: liveins: $x10
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x11 = ADDI $x10, 384
+ ; RV32C-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx)
+ ; RV32C-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1)
+ ; RV32C-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2)
+ ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ;
; RV64-LABEL: name: load_large_offset_float
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -758,6 +944,23 @@ body: |
; RV64-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
; RV64-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ;
+ ; RV32ZCF-LABEL: name: load_large_offset_float
+ ; RV32ZCF: liveins: $x10
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: $x11 = ADDI $x10, 384
+ ; RV32ZCF-NEXT: renamable $f10_f = FLW $x11, 16 :: (load (s32) from %ir.arrayidx)
+ ; RV32ZCF-NEXT: renamable $f11_f = FLW $x11, 20 :: (load (s32) from %ir.arrayidx1)
+ ; RV32ZCF-NEXT: renamable $f12_f = FLW killed $x11, 24 :: (load (s32) from %ir.arrayidx2)
+ ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
+ ;
+ ; RV32ZCA-LABEL: name: load_large_offset_float
+ ; RV32ZCA: liveins: $x10
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
+ ; RV32ZCA-NEXT: renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
+ ; RV32ZCA-NEXT: renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
+ ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_float_1, implicit $x2, implicit $f10_f, implicit $f11_f, implicit $f12_f
renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
renamable $f11_f = FLW renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
renamable $f12_f = FLW killed renamable $x10, 408 :: (load (s32) from %ir.arrayidx2)
@@ -771,22 +974,47 @@ body: |
bb.0.entry:
liveins: $x10
- ; RV32-LABEL: name: load_large_offset_double
- ; RV32: liveins: $x10
- ; RV32-NEXT: {{ $}}
- ; RV32-NEXT: $x11 = ADDI $x10, 768
- ; RV32-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
- ; RV32-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
- ; RV32-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
- ; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
- ; RV64-LABEL: name: load_large_offset_double
- ; RV64: liveins: $x10
- ; RV64-NEXT: {{ $}}
- ; RV64-NEXT: $x11 = ADDI $x10, 768
- ; RV64-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
- ; RV64-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
- ; RV64-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
- ; RV64-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ; RV32C-LABEL: name: load_large_offset_double
+ ; RV32C: liveins: $x10
+ ; RV32C-NEXT: {{ $}}
+ ; RV32C-NEXT: $x11 = ADDI $x10, 768
+ ; RV32C-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
+ ; RV32C-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
+ ; RV32C-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
+ ; RV32C-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV64C-LABEL: name: load_large_offset_double
+ ; RV64C: liveins: $x10
+ ; RV64C-NEXT: {{ $}}
+ ; RV64C-NEXT: $x11 = ADDI $x10, 768
+ ; RV64C-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
+ ; RV64C-NEXT: renamable $f11_d = FLD $x11, 40 :: (load (s64) from %ir.arrayidx1)
+ ; RV64C-NEXT: renamable $f12_d = FLD killed $x11, 48 :: (load (s64) from %ir.arrayidx2)
+ ; RV64C-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV32ZCF-LABEL: name: load_large_offset_double
+ ; RV32ZCF: liveins: $x10
+ ; RV32ZCF-NEXT: {{ $}}
+ ; RV32ZCF-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
+ ; RV32ZCF-NEXT: renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
+ ; RV32ZCF-NEXT: renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2)
+ ; RV32ZCF-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV32ZCA-LABEL: name: load_large_offset_double
+ ; RV32ZCA: liveins: $x10
+ ; RV32ZCA-NEXT: {{ $}}
+ ; RV32ZCA-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
+ ; RV32ZCA-NEXT: renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
+ ; RV32ZCA-NEXT: renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2)
+ ; RV32ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
+ ;
+ ; RV64ZCA-LABEL: name: load_large_offset_double
+ ; RV64ZCA: liveins: $x10
+ ; RV64ZCA-NEXT: {{ $}}
+ ; RV64ZCA-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
+ ; RV64ZCA-NEXT: renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
+ ; RV64ZCA-NEXT: renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2)
+ ; RV64ZCA-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, implicit $x2, implicit $f10_d, implicit $f11_d, implicit $f12_d
renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
renamable $f12_d = FLD killed renamable $x10, 816 :: (load (s64) from %ir.arrayidx2)
@@ -805,6 +1033,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: SW $x0, killed renamable $x10, 0 :: (store (s32) into %ir.a)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_value_no_opt
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -826,6 +1055,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: FSW killed renamable $f16_f, killed renamable $x10, 0 :: (store (s32) into %ir.a)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_value_float_no_opt
; RV64: liveins: $x10, $f16_f
; RV64-NEXT: {{ $}}
@@ -847,6 +1077,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: FSD killed renamable $f16_d, killed renamable $x10, 0 :: (store (s64) into %ir.a)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_value_double_no_opt
; RV64: liveins: $x10, $f16_d
; RV64-NEXT: {{ $}}
@@ -869,6 +1100,7 @@ body: |
; RV32-NEXT: renamable $x10 = ADDI $x0, 1
; RV32-NEXT: SW killed renamable $x10, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_ptr_no_opt
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -892,6 +1124,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: FSW killed renamable $f10_f, killed renamable $x16, 0 :: (volatile store (s32) into %ir.p)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_ptr_float_no_opt
; RV64: liveins: $x16, $f10_f
; RV64-NEXT: {{ $}}
@@ -913,6 +1146,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: FSD killed renamable $f10_d, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_common_ptr_double_no_opt
; RV64: liveins: $x16, $f10_d
; RV64-NEXT: {{ $}}
@@ -934,6 +1168,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: dead renamable $x10 = LW killed renamable $x16, 0 :: (volatile load (s32) from %ir.p)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: load_common_ptr_no_opt
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -955,6 +1190,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: renamable $f10_f = FLW killed renamable $x16, 0 :: (load (s32) from %ir.g)
; RV32-NEXT: PseudoRET implicit $f10_f
+ ;
; RV64-LABEL: name: load_common_ptr_float_no_opt
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -976,6 +1212,7 @@ body: |
; RV32-NEXT: {{ $}}
; RV32-NEXT: renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g)
; RV32-NEXT: PseudoRET implicit $f10_d
+ ;
; RV64-LABEL: name: load_common_ptr_double_no_opt
; RV64: liveins: $x16
; RV64-NEXT: {{ $}}
@@ -1000,6 +1237,7 @@ body: |
; RV32-NEXT: renamable $x11 = ADDI $x0, 3
; RV32-NEXT: SW killed renamable $x11, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_large_offset_no_opt
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -1028,6 +1266,7 @@ body: |
; RV32-NEXT: FSW killed renamable $f10_f, renamable $x10, 400 :: (volatile store (s32) into %ir.0)
; RV32-NEXT: FSW killed renamable $f11_f, killed renamable $x10, 404 :: (volatile store (s32) into %ir.1)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_large_offset_float_no_opt
; RV64: liveins: $x10, $f10_f, $f11_f
; RV64-NEXT: {{ $}}
@@ -1052,6 +1291,7 @@ body: |
; RV32-NEXT: FSD killed renamable $f10_d, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
; RV32-NEXT: FSD killed renamable $f11_d, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: store_large_offset_double_no_opt
; RV64: liveins: $x10, $f10_d, $f11_d
; RV64-NEXT: {{ $}}
@@ -1076,6 +1316,7 @@ body: |
; RV32-NEXT: dead renamable $x11 = LW renamable $x10, 400 :: (volatile load (s32) from %ir.0)
; RV32-NEXT: dead renamable $x10 = LW killed renamable $x10, 404 :: (volatile load (s32) from %ir.1)
; RV32-NEXT: PseudoRET
+ ;
; RV64-LABEL: name: load_large_offset_no_opt
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -1100,6 +1341,7 @@ body: |
; RV32-NEXT: renamable $f10_f = FLW renamable $x10, 400 :: (load (s32) from %ir.arrayidx)
; RV32-NEXT: renamable $f11_f = FLW killed renamable $x10, 404 :: (load (s32) from %ir.arrayidx1)
; RV32-NEXT: PseudoRET implicit $f10_f, implicit $f11_f
+ ;
; RV64-LABEL: name: load_large_offset_float_no_opt
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
@@ -1124,6 +1366,7 @@ body: |
; RV32-NEXT: renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
; RV32-NEXT: renamable $f11_d = FLD killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
; RV32-NEXT: PseudoRET implicit $f10_d, implicit $f11_d
+ ;
; RV64-LABEL: name: load_large_offset_double_no_opt
; RV64: liveins: $x10
; RV64-NEXT: {{ $}}
>From ff288167bb9dce2a5825bb48da97ae396e5dab8b Mon Sep 17 00:00:00 2001
From: Yeting Kuo <yeting.kuo at sifive.com>
Date: Wed, 21 Feb 2024 22:53:16 -0800
Subject: [PATCH 3/3] Address Craig's comment
---
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index 6759be63d46bab..af864ba0fbc46f 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -340,7 +340,7 @@ bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
const RISCVInstrInfo &TII = *STI.getInstrInfo();
// This optimization only makes sense if compressed instructions are emitted.
- if (!STI.hasStdExtZca() && !STI.hasStdExtCOrZcfOrZce() && !STI.hasStdExtZcd())
+ if (!STI.hasStdExtCOrZca())
return false;
for (MachineBasicBlock &MBB : Fn) {
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