[llvm] [RISCV][VP] Introduce vp saturating addition/substraction and RISC-V support. (PR #82370)

[Yeting Kuo via llvm-commits]

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@@ -945,9 +954,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
   SDLoc dl(N);
   SDValue Op1 = N->getOperand(0);
   SDValue Op2 = N->getOperand(1);
+  MatchContextClass matcher(DAG, TLI, N);
   unsigned OldBits = Op1.getScalarValueSizeInBits();
 
-  unsigned Opcode = N->getOpcode();
+  unsigned Opcode = matcher.getRootBaseOpcode();
   bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
 
   SDValue Op1Promoted, Op2Promoted;
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yetingk wrote:

I added a FIXME for this instead to fix it in this PR. Is it Ok?

https://github.com/llvm/llvm-project/pull/82370