[llvm] [AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (PR #82245)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 19 05:08:45 PST 2024
https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/82245
Using OtherPredicates for True16 predicates is often problematic due to interference with other kinds of predicates, particularly when this overrides predicates inherited from pseudo instructions.
>From b28fd9b85664532e34cabf7161606257e604ee00 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Mon, 19 Feb 2024 12:44:09 +0000
Subject: [PATCH] [AMDGPU][NFC] Extend PredicateControl to support True16
predicates.
Using OtherPredicates for True16 predicates is often problematic due to
interference with other kinds of predicates, particularly when this
overrides predicates inherited from pseudo instructions.
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 7 ++--
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 22 ------------
.../Target/AMDGPU/AMDGPUPredicateControl.td | 36 +++++++++++++++++++
llvm/lib/Target/AMDGPU/R600.td | 1 +
llvm/lib/Target/AMDGPU/VOPInstructions.td | 4 +--
5 files changed, 43 insertions(+), 27 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUPredicateControl.td
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index b29dc1edbaaff9..7c278fd574ede5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -9,6 +9,7 @@
include "llvm/TableGen/SearchableTable.td"
include "llvm/Target/Target.td"
include "AMDGPUFeatures.td"
+include "AMDGPUPredicateControl.td"
def p0 : PtrValueType<i64, 0>;
def p1 : PtrValueType<i64, 1>;
@@ -1895,10 +1896,10 @@ def NotHasTrue16BitInsts : Predicate<"!Subtarget->hasTrue16BitInsts()">;
// True16 instructions as they are defined in the ISA. Fake True16
// instructions have the same encoding as real ones but syntactically
// only allow 32-bit registers in operands and use low halves thereof.
-def UseRealTrue16Insts : Predicate<"Subtarget->useRealTrue16Insts()">,
+def UseRealTrue16Insts : True16PredicateClass<"Subtarget->useRealTrue16Insts()">,
AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts)>;
-def UseFakeTrue16Insts : Predicate<"Subtarget->hasTrue16BitInsts() && "
- "!Subtarget->useRealTrue16Insts()">;
+def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() && "
+ "!Subtarget->useRealTrue16Insts()">;
def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
AssemblerPredicate<(all_of FeatureVOP3P)>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 360aafedc52248..5ed82c0c4b1b8e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -76,33 +76,11 @@ class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
let isCodeGenOnly = 1;
}
-def TruePredicate : Predicate<"">;
-
-// FIXME: Tablegen should specially supports this
-def FalsePredicate : Predicate<"false">;
-
-// Add a predicate to the list if does not already exist to deduplicate it.
-class PredConcat<list<Predicate> lst, Predicate pred> {
- list<Predicate> ret = !listconcat(lst, !listremove([pred], lst));
-}
-
// Get the union of two Register lists
class RegListUnion<list<Register> lstA, list<Register> lstB> {
list<Register> ret = !listconcat(lstA, !listremove(lstB, lstA));
}
-class PredicateControl {
- Predicate SubtargetPredicate = TruePredicate;
- Predicate AssemblerPredicate = TruePredicate;
- Predicate WaveSizePredicate = TruePredicate;
- list<Predicate> OtherPredicates = [];
- list<Predicate> Predicates = PredConcat<
- PredConcat<PredConcat<OtherPredicates,
- SubtargetPredicate>.ret,
- AssemblerPredicate>.ret,
- WaveSizePredicate>.ret;
-}
-
class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
PredicateControl, GISelFlags;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPredicateControl.td b/llvm/lib/Target/AMDGPU/AMDGPUPredicateControl.td
new file mode 100644
index 00000000000000..6c7c91ef464dfd
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPredicateControl.td
@@ -0,0 +1,36 @@
+//===-- AMDGPUPredicateControl.td --------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+def TruePredicate : Predicate<"">;
+
+// FIXME: Tablegen should specially supports this
+def FalsePredicate : Predicate<"false">;
+
+// Add a predicate to the list if does not already exist to deduplicate it.
+class PredConcat<Predicate pred, list<Predicate> lst> {
+ list<Predicate> ret = !listconcat(lst, !listremove([pred], lst));
+}
+
+// Prevent using other kinds of predicates where True16 predicates are
+// expected by giving them their own class.
+class True16PredicateClass<string cond> : Predicate<cond>;
+def NoTrue16Predicate : True16PredicateClass<"">;
+
+class PredicateControl {
+ Predicate SubtargetPredicate = TruePredicate;
+ Predicate AssemblerPredicate = TruePredicate;
+ Predicate WaveSizePredicate = TruePredicate;
+ True16PredicateClass True16Predicate = NoTrue16Predicate;
+ list<Predicate> OtherPredicates = [];
+ list<Predicate> Predicates =
+ PredConcat<SubtargetPredicate,
+ PredConcat<AssemblerPredicate,
+ PredConcat<WaveSizePredicate,
+ PredConcat<True16Predicate,
+ OtherPredicates>.ret>.ret>.ret>.ret;
+}
diff --git a/llvm/lib/Target/AMDGPU/R600.td b/llvm/lib/Target/AMDGPU/R600.td
index 1e8e6f34fbc0cd..9148edb92b084d 100644
--- a/llvm/lib/Target/AMDGPU/R600.td
+++ b/llvm/lib/Target/AMDGPU/R600.td
@@ -35,6 +35,7 @@ include "R600Schedule.td"
include "R600Processors.td"
include "R600InstrInfo.td"
include "AMDGPUInstrInfo.td"
+include "AMDGPUPredicateControl.td"
include "AMDGPUInstructions.td"
include "R600Instructions.td"
include "R700Instructions.td"
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index dc6a48b1df7472..29c30bc019ed63 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -1484,8 +1484,8 @@ multiclass VOP3_Real_dpp8_with_name<GFXGen Gen, bits<10> op, string opName,
let AsmString = asmName # ps.Pfl.AsmVOP3DPP8,
DecoderNamespace = "DPP8"#Gen.DecoderNamespace#
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16"),
- OtherPredicates = !if(ps.Pfl.IsRealTrue16, [UseRealTrue16Insts],
- [TruePredicate]) in {
+ True16Predicate = !if(ps.Pfl.IsRealTrue16, UseRealTrue16Insts,
+ NoTrue16Predicate) in {
defm NAME : VOP3_Real_dpp8_Base<Gen, op, opName>;
}
}
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