The Week Of Monday 23 February 2026 Archives by thread
Starting: Mon Feb 23 00:05:24 PST 2026
Ending: Sat Feb 28 22:11:15 PST 2026
Messages: 5806
- [llvm] [OpenMP][Offload] Handle `present/to/from` when a different entry did `alloc/delete`. (PR #165494)
Robert Imschweiler via llvm-commits
- [llvm] [NFCI][VPlan] Split initial mem-widening into a separate transformation (PR #182592)
Ramkumar Ramachandra via llvm-commits
- [llvm] [VPlan] Prevent uses of materialized VPSymbolicValues. (NFC) (PR #182318)
Ramkumar Ramachandra via llvm-commits
- [llvm] [AArch64] Add basic scmp and ucmp costs. (PR #182180)
David Green via llvm-commits
- [llvm] [Hexagon] Disable new value jumps when packetizer is disabled (PR #180615)
Cullen Rhodes via llvm-commits
- [llvm] [Hexagon] Fix extractHvxSubvectorPred shuffle mask for small predicates (PR #181364)
Cullen Rhodes via llvm-commits
- [llvm] [InstCombine] Only ignore first zero index during GEP canonicalization (PR #180764)
Nikita Popov via llvm-commits
- [llvm] [AMDGPU][GlobalISel] Update G_TRUNC tests (PR #180647)
Anshil Gandhi via llvm-commits
- [llvm] cb3d7ff - [AArch64] Add bfloat patterns for `partial_reduce_fmla` (#181982)
via llvm-commits
- [llvm] [AArch64] Add bfloat patterns for `partial_reduce_fmla` (PR #181982)
Benjamin Maxwell via llvm-commits
- [clang] [llvm] [clang][DebugInfo] Add virtuality call-site target information in DWARF. (PR #182510)
Carlos Alberto Enciso via llvm-commits
- [llvm] [Hexagon] Add AggressiveRDF copy propagation (PR #182818)
Yashas Andaluri via llvm-commits
- [llvm] [WebAssembly][FastISel] Emit signed loads for sext of i8/i16/i32 (PR #182767)
via llvm-commits
- [llvm] [CMake] Don't try to reuse PCH if PCH is disabled (PR #182819)
Alexis Engelke via llvm-commits
- [llvm] ca7cf83 - [Maintainers] Fix broken clang link (NFC) (#182451)
via llvm-commits
- [llvm] [Maintainers] Fix broken clang link (NFC) (PR #182451)
Cullen Rhodes via llvm-commits
- [llvm] 53648f5 - [AArch64] -aarch64-enable-global-isel-at-O=-1 should disable GISel (#182250)
via llvm-commits
- [llvm] [AArch64] -aarch64-enable-global-isel-at-O=-1 should disable GISel (PR #182250)
Cullen Rhodes via llvm-commits
- [clang] [flang] [llvm] [mlir] [polly] [CMake][LLVM] Add PCH infrastructure and LLVMSupport PCH (PR #176420)
Alexis Engelke via llvm-commits
- [llvm] [VPlan][NFC] Extract addCurrentIterationPhi from addExplicitVectorLength (PR #182650)
Shih-Po Hung via llvm-commits
- [llvm] [M68k] Update llvm/test/CodeGen/M68k/pipeline.ll (PR #182809)
Nikita Popov via llvm-commits
- [llvm] 63e3e89 - [InstCombine] Only ignore first zero index during GEP canonicalization (#180764)
via llvm-commits
- [llvm] [VPlan] Optimize resume values of IVs together with other exit values. (PR #174239)
Florian Hahn via llvm-commits
- [llvm] [RISCV] Add contraints for SpacemiT X60 AI VDot Insts (PR #174364)
via llvm-commits
- [llvm] [LV] Add flag to always force a scalable VF when feasible. (PR #182467)
Florian Hahn via llvm-commits
- [llvm] [AMDGPU]Implement get addr space cast preserved ptr mask (PR #182658)
via llvm-commits
- [clang] [compiler-rt] [flang] [libc] [libcxx] [lldb] [llvm] [RFC][Clang] Add __int256/__uint256 builtin types (PR #182733)
Xavier Roche via llvm-commits
- [llvm] [mlir] [OMPIRBuilder] Replace getAllocatedType with getAllocationSize (PR #181844)
Jack Styles via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Luke Lau via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Luke Lau via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Luke Lau via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Luke Lau via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Luke Lau via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Ramkumar Ramachandra via llvm-commits
- [llvm] [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (PR #182684)
Craig Topper via llvm-commits
- [llvm] [SPARC] Add TTI implementation for getting register numbers and widths (PR #180660)
via llvm-commits
- [llvm] [ARM] Explicitly mark certain instructions as having no side effects. (PR #182771)
David Green via llvm-commits
- [llvm] [AArch64] optimize manual pairwise min/max (PR #182785)
Folkert de Vries via llvm-commits
- [llvm] 3849fce - [CMake] Don't try to reuse PCH if PCH is disabled (#182819)
via llvm-commits
- [llvm] [AArch64][GlobalISel] FP Info implementation for AArch64. (PR #177158)
David Green via llvm-commits
- [clang] [llvm] [cmake] Add config for riscv(32|64)-unknown-elf (PR #176353)
Ramkumar Ramachandra via llvm-commits
- [llvm] [AMDGPU] Move `advanceBeforeNext` before `advanceToNext` (PR #182808)
Lucas Ramirez via llvm-commits
- [llvm] [VPlan] Remove verifyEVLRecipe (PR #182798)
Florian Hahn via llvm-commits
- [llvm] [AMDGPU] Add regbank legalization rules for G_ATOMICRMW_FMIN and G_ATOMICRMW_FMAX (PR #182824)
Anshil Gandhi via llvm-commits
- [llvm] f02aadc - [AArch64][GlobalISel] Combine to sqxtn pre legalization for FewerElements (#181163)
via llvm-commits
- [llvm] [AArch64][GlobalISel] Combine to sqxtn pre legalization for FewerElements (PR #181163)
David Green via llvm-commits
- [llvm] Provide intrinsics for speculative loads (PR #179642)
Florian Hahn via llvm-commits
- [clang] [lld] [llvm] [WebAssembly] WASIP3 and component model threading support (PR #175800)
Sy Brand via llvm-commits
- [llvm] 279b3db - [InstCombine] Fold icmp (vreduce_(or|and) %x), (0|-1) (#182684)
via llvm-commits
- [llvm] 5870fcf - [M68k] Update llvm/test/CodeGen/M68k/pipeline.ll (#182809)
via llvm-commits
- [llvm] [ISel/RISCV] Scalarize small pow-of-2 VECREDUCE_(AND|OR|XOR) (PR #182631)
Ramkumar Ramachandra via llvm-commits
- [llvm] [libsycl] add sycl::context stub (PR #182826)
Kseniya Tikhomirova via llvm-commits
- [llvm] [RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (PR #182456)
via llvm-commits
- [llvm] [VPlan] Use bitfield to store Cmp predicates and GEP wrap flags. (NFC) (PR #181571)
Ramkumar Ramachandra via llvm-commits
- [llvm] [TableGen] fix unreachable code warning in *GenSubtargetInfo.inc files (PR #182477)
Jay Foad via llvm-commits
- [llvm] [Semilattice] Introduce for dataflow analysis with KnownBits (PR #177616)
Ramkumar Ramachandra via llvm-commits
- [llvm] [VectorCombine] Support ashr sign-bit extraction (PR #181998)
Valeriy Savchenko via llvm-commits
- [llvm] [BOLT][BTI] Patch ignored functions in place when targeting them with indirect branches (PR #177165)
Paschalis Mpeis via llvm-commits
- [llvm] [libsycl] Fix for static vars deinit order (libsycl vs liboffload) (PR #181366)
Kseniya Tikhomirova via llvm-commits
- [llvm] 4bd0e49 - [VPlan] Remove verifyEVLRecipe (#182798)
via llvm-commits
- [lldb] [llvm] [lldb][ARM] Support reading the thread pointer register on ARM Linux (PR #182438)
David Spickett via llvm-commits
- [llvm] [ConstantTime][LLVM] Add llvm.ct.select intrinsic with generic SelectionDAG lowering (PR #166702)
Simon Tatham via llvm-commits
- [llvm] [llvm-symbolizer] Make symbolizer parse section relative syntax (PR #168524)
via llvm-commits
- [llvm] FunctionAttrs: Basic propagation of nofpclass (PR #182444)
Matt Arsenault via llvm-commits
- [llvm] [X86] Attempt to use VPMADD52L/VPMULUDQ instead of VPMULLQ on slow VPMULLQ targets (or when VPMULLQ is unavailable) (PR #171760)
Simon Pilgrim via llvm-commits
- [llvm] [LV] Add corner-case tests for licm of predicated memops (PR #182828)
Ramkumar Ramachandra via llvm-commits
- [llvm] [AArch64] Add C1-Nano scheduling model (PR #182316)
via llvm-commits
- [llvm] [VPlan] Remove verifyLate from VPlanVerifier. NFC (PR #182799)
Luke Lau via llvm-commits
- [clang] [flang] [llvm] [InstCombine] Canonicalize GEP source element types (PR #180745)
Nikita Popov via llvm-commits
- [llvm] [AMDGPU][ISel] Reduce 64-bit `setcc` to upper 32 bits if lower 32 bits are known (PR #181238)
Jay Foad via llvm-commits
- [llvm] AMDGPU/GlobalISel: Regbanklegalize rules for G_PHI (PR #179735)
Petar Avramovic via llvm-commits
- [llvm] 594e889 - [PowerPC] Fix duplicate RUN lines in tests (#182275)
via llvm-commits
- [llvm] [PowerPC] Fix duplicate RUN lines in tests (PR #182275)
Jay Foad via llvm-commits
- [llvm] [X86] Add i256/i512 CTPOP expansion on AVX512VPOPCNTDQ targets (PR #182830)
Simon Pilgrim via llvm-commits
- [llvm] [AMDGPU] [GlobalISel] Add register bank legalize rules for G_FEXP2 (PR #179954)
Petar Avramovic via llvm-commits
- [llvm] [DAG] isKnownNeverZero - add DemandedElts argument (PR #182679)
via llvm-commits
- [clang] [flang] [llvm] [mlir] [OpenMP] Only generate call to __kmpc_global_thread_num when needed (PR #182669)
Tom Eccles via llvm-commits
- [llvm] [LAA][LV]Allow recognition of strided pointers with constant stride (PR #171151)
Nashe Mncube via llvm-commits
- [lld] 3fc9018 - Revert "CodeGen: Emit .prefalign directives based on the prefalign attribute."
Nikita Popov via llvm-commits
- [clang] [lld] [llvm] CodeGen: Emit .prefalign directives based on the prefalign attribute. (PR #155529)
Nikita Popov via llvm-commits
- [lld] [ELF] Add target-specific relocation scanning for ARM (PR #182440)
Peter Smith via llvm-commits
- [llvm] [DAG] TargetLowering::expandCLMUL - avoid ISD::MUL if target hasBitTest (PR #177566)
Simon Pilgrim via llvm-commits
- [llvm] [GlobalISel] Combine sext(load), zext(load) patterns when the load has multiple uses (PR #182831)
via llvm-commits
- [llvm] [TableGen] Add let append/prepend syntax for field concatenation (PR #182382)
Mehdi Amini via llvm-commits
- [llvm] [SPIR-V] Fix non-deterministic compiler output for debug type pointer (PR #182773)
Manuel Carrasco via llvm-commits
- [llvm] [SPIR-V] Don't consider a function be a builtin just by checking name (PR #182776)
Viktoria Maximova via llvm-commits
- [lld] [LLD][ELF][RISCV] Support big-endian RISC-V linking (PR #180912)
Djordje Todorovic via llvm-commits
- [llvm] [SPIR-V] Add lowering for G_FEXP10 (PR #182466)
Juan Manuel Martinez Caamaño via llvm-commits
- [llvm] [AMDGPU] Add VOPD to gfx13 (PR #182815)
Matt Arsenault via llvm-commits
- [llvm] [TableGen] Implement TypesAreContradictory for non-simple ValueTypeByHwMode. (PR #182765)
Matt Arsenault via llvm-commits
- [llvm] [X86] Add test coverage for #137422 (PR #182832)
Simon Pilgrim via llvm-commits
- [llvm] [InstCombine] Restrict foldICmpOfVectorReduce to one-use (PR #182833)
Ramkumar Ramachandra via llvm-commits
- [llvm] [VPlan] Simplify ExitingIVValue and use for tail-folded IVs. (PR #182507)
Luke Lau via llvm-commits
- [llvm] [NFCi][AsmPrinter] Refactor getting analyses to callbacks (PR #182793)
Diana Picus via llvm-commits
- [llvm] [RISCV] Rename RVVConstraint->VS1VS2Constraint. NFC (PR #182688)
Luke Lau via llvm-commits
- [llvm] [DAG] Improved handling of ISD::ROTL and ISD::ROTR in isKnownToBeAPowerOfTwo (PR #182744)
Matt Arsenault via llvm-commits
- [llvm] [NFC][AMDGPU] Add test showing caller/callee SGPR mismatch for inreg args (PR #182753)
Matt Arsenault via llvm-commits
- [llvm] [VPlan] Move tail folding out of VPlanPredicator. NFC (PR #176143)
Luke Lau via llvm-commits
- [llvm] [vim] Set commentstring for TableGen files (PR #182654)
Fraser Cormack via llvm-commits
- [llvm] [AMDGPU] Add VFLAT, VGLOBAL, VSCRATCH to gfx13 (PR #182811)
Matt Arsenault via llvm-commits
- [llvm] [mlir] [MLIR][OpenMP] Remove Generic-SPMD early detection (PR #150922)
Sergio Afonso via llvm-commits
- [clang] [llvm] [analyzer] New checker: optin.core.UnconditionalVAArg (PR #175602)
Donát Nagy via llvm-commits
- [llvm] 36d60b1 - [analyzer] New checker: optin.core.UnconditionalVAArg (#175602)
via llvm-commits
- [llvm] Reapply "[ValueTracking] Propagate sign information out of loop" (PR #182512)
Kshitij Paranjape via llvm-commits
- [llvm] [ValueTracking] Conservative nosync check prevents vectorization (PR #181345)
Kshitij Paranjape via llvm-commits
- [llvm] [TTI] Provide conservative costs for @llvm.speculative.load. (PR #180036)
Florian Hahn via llvm-commits
- [llvm] [mlir] [mlir] Replace MLIR_ENABLE_ROCM_CONVERSIONS with LLVM_HAS_AMDGPU_TARGET (PR #182652)
Mehdi Amini via llvm-commits
- [llvm] [LV] Fix miscompile with conditional scalar assignment + tail folding (PR #182492)
Graham Hunter via llvm-commits
- [llvm] [SPIR-V] Stop emitting FPRoundingMode for arithmetic constrained intrinsics (PR #182742)
Juan Manuel Martinez Caamaño via llvm-commits
- [llvm] 0e3a96d - [X86] Add test coverage for #137422 (#182832)
via llvm-commits
- [llvm] [SLP]Remove Alternate early profitability checks in favor of throttling (PR #182760)
Simon Pilgrim via llvm-commits
- [llvm] [SLP]Initial support for ordered reductions (PR #182644)
Simon Pilgrim via llvm-commits
- [compiler-rt] [scudo] Change header tagging for the secondary allocator (PR #182487)
Tamas Kaman via llvm-commits
- [llvm] [VPlan] Handle early exit loops with non-dereferenceable loads in latch (PR #172454)
Luke Lau via llvm-commits
- [llvm] [AMDGPU] Add VOP2 to gfx13 (PR #182812)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] Remove AMDGPUArgumentUsageInfo pass (PR #182490)
Matt Arsenault via llvm-commits
- [llvm] [LangRef] Mention allocation elision (PR #177592)
Ralf Jung via llvm-commits
- [clang] [clang-tools-extra] [llvm] [WebAssembly][Sanitizer] WebAssembly Memory Tagging (PR #162972)
via llvm-commits
- [llvm] [DAG] isKnownToBeAPowerOfTwo - Power of 2 value is known to be power of 2 after BSWAP/BITREVERSE (PR #182207)
Simon Pilgrim via llvm-commits
- [llvm] [AArch64] Fix regression from “Fold scalar-to-vector shuffles into DUP/FMOV" (PR #178227)
Amina Chabane via llvm-commits
- [llvm] [CI] Enable OpenMP and Offload runtime in premerge (PR #174955)
Jan Patrick Lehr via llvm-commits
- [llvm] FunctionAttrs: Do not infer top down on functions with no uses (PR #182839)
Matt Arsenault via llvm-commits
- [llvm] Improved ISD::SRL handling in isKnownToBeAPowerOfTwo (PR #182562)
Simon Pilgrim via llvm-commits
- [llvm] [LoopUnroll] Support parallel reductions for minmax (PR #182473)
Florian Hahn via llvm-commits
- [llvm] [NFC][SPARC] Add proper flags for instruction definitions (PR #182840)
via llvm-commits
- [llvm] [SimplifyCFG] remove misleading arrow operator (PR #182435)
Congcong Cai via llvm-commits
- [clang] [compiler-rt] [llvm] [X86] Add AVX512BMM support for AMD Zen 6 (znver6) (PR #182556)
Simon Pilgrim via llvm-commits
- [llvm] Re-enable MSVC C4141 diagnostic; NFC (PR #182586)
Aaron Ballman via llvm-commits
- [llvm] Support non-constant `G_BUILD_VECTOR` in X86. (PR #182502)
Simon Pilgrim via llvm-commits
- [llvm] [NFC][IR] Fix MSVC C4706 diagnostic w/ 741b2cda32e1 (PR #182682)
Aaron Ballman via llvm-commits
- [llvm] [X86] Fold XOR of two vgf2p8affineqb instructions with same input (PR #179900)
Simon Pilgrim via llvm-commits
- [llvm] 966a461 - [VectorCombine] Support ashr sign-bit extraction (#181998)
via llvm-commits
- [llvm] [LIBM][AMDLIBM] - Add new vector call support for fveclib=AMDLIBM (PR #180896)
Simon Pilgrim via llvm-commits
- [llvm] [NFCI][AMDGPU] Use X-macro to reduce boilerplate in `GCNSubtarget.h` (PR #176844)
Tim Renouf via llvm-commits
- [llvm] [GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (PR #155107)
via llvm-commits
- [llvm] [NFC][AArch64] Split fptoi tests and add scal_to_vec convert tests (PR #179315)
via llvm-commits
- [llvm] [AArch64][PAC] Don't skip global legalization for AUTH_TCRETURN (PR #182513)
via llvm-commits
- [llvm] 9e6a6be - [AMDGPU] Remove AMDGPUArgumentUsageInfo pass (#182490)
via llvm-commits
- [llvm] [SPIRV][NFC] Update tests to check `spirv-val` output (PR #182549)
Viktoria Maximova via llvm-commits
- [llvm] Add EVT::changeVectorElementCount and MVT:changeVectorElementCount (PR #182266)
Chaitanya Koparkar via llvm-commits
- [llvm] 8b36a41 - FunctionAttrs: Do not infer top down on functions with no uses (#182839)
via llvm-commits
- [llvm] [SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (PR #145902)
Björn Pettersson via llvm-commits
- [llvm] 5e5e300 - [SelectionDAG] Fix bug related to demanded bits/elts for BITCAST (#145902)
via llvm-commits
- [llvm] Add DoNotPoisonEltMask to several SimplifyDemanded function in TargetLowering (PR #145903)
Björn Pettersson via llvm-commits
- [llvm] [tools] llvm-advisor: LLVM compiler visualization tool for offloading (PR #147451)
Miguel Cárdenas via llvm-commits
- [llvm] Re-enable MSVC C4722 diagnostic; NFC (PR #182845)
Aaron Ballman via llvm-commits
- [llvm] [IR] Add initial support for the byte type (PR #178666)
Nikita Popov via llvm-commits
- [clang] [llvm] [CIR][NFC] Add skeleton for target-specific lowering (PR #182645)
Sirui Mu via llvm-commits
- [llvm] [LangRef] Specify semantics for non-byte-sized loads and stores (PR #180739)
Nikita Popov via llvm-commits
- [llvm] [AArch64] Optimize 64-bit constant vector builds (PR #177076)
David Green via llvm-commits
- [llvm] [Offload] Fix copy-elision warning (PR #182848)
Jan Patrick Lehr via llvm-commits
- [llvm] [X86] getFauxShuffleMask - OR(SHUF(),SHUF()) - treat undemanded elements as undef (PR #182678)
Phoebe Wang via llvm-commits
- [llvm] [WebAssembly] optimize ext + shuffle + add into addext (PR #182849)
Folkert de Vries via llvm-commits
- [llvm] [NFC][AArch64] AArch64ConditionOptimizer extract shared instruction finding logic (PR #182244)
Nashe Mncube via llvm-commits
- [llvm] [ARM] optimize to `vsri`/`vsli` (PR #182051)
David Green via llvm-commits
- [llvm] [X86] lowerV64I8Shuffle - prefer VPERMV3 byte shuffles to OR(PSHUFB,PSHUFB) on VBMI targets (PR #182852)
Simon Pilgrim via llvm-commits
- [llvm] [DSE] Consider all dominating conditions in `dominatingConditionImpliesValue` (PR #181709)
Antonio Frighetto via llvm-commits
- [llvm] [DSE] Introduce `eliminateRedundantStoresViaDominatingConditions` (PR #181709)
Antonio Frighetto via llvm-commits
- [llvm] [LLVM] Refine MemoryEffect handling for target-specific intrinsics (PR #155590)
via llvm-commits
- [llvm] [AMDGPU][Scheduler] Add `GCNRegPressure`-based methods to `GCNRPTarget` (PR #182853)
Lucas Ramirez via llvm-commits
- [llvm] 630a418 - Re-enable MSVC C4141 diagnostic; NFC (#182586)
via llvm-commits
- [llvm] 1737b61 - Re-enable MSVC C4722 diagnostic; NFC (#182845)
via llvm-commits
- [llvm] [AArch64] Cortex-A55/A320/A510 scheduling model "typo" fixes (PR #182854)
via llvm-commits
- [llvm] [RISCV] Make ElementsDependOn opt-in instead of opt-out. NFCI (PR #181601)
Luke Lau via llvm-commits
- [llvm] 817b7f3 - [NFC][AArch64] Split fptoi tests and add scal_to_vec convert tests (#179315)
via llvm-commits
- [llvm] [LLVM][PDB] Add missing type/symbol IDs (PR #182743)
via llvm-commits
- [llvm] [VPlan] Add the cost of spills when considering register pressure (PR #179646)
Luke Lau via llvm-commits
- [llvm] [AArch64] Wrap integer SCALAR_TO_VECTOR nodes in bitcasts (PR #172837)
via llvm-commits
- [llvm] [AArch64] C1-Ultra Scheduling model (PR #182251)
Nashe Mncube via llvm-commits
- [llvm] [Hexagon] Handle subreg copies between DoubleRegs and IntRegs (PR #181360)
Krzysztof Parzyszek via llvm-commits
- [llvm] 8f5880d - [X86] lowerV64I8Shuffle - prefer VPERMV3 byte shuffles to OR(PSHUFB,PSHUFB) on VBMI targets (#182852)
via llvm-commits
- [llvm] [AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (PR #182107)
Mirko Brkušanin via llvm-commits
- [llvm] [AMDGPU][True16] change vdst_in regclass for cvt_pk_f8_fp32 pattern (PR #179995)
Brox Chen via llvm-commits
- [llvm] [AArch64] Match CTPOP combine without zero extend (PR #182859)
Benjamin Maxwell via llvm-commits
- [llvm] [LV] NFCI: Move extend optimization to transformToPartialReduction. (PR #182860)
Sander de Smalen via llvm-commits
- [llvm] [VPlan] Supported conditionally executed single early exits. (PR #182395)
Luke Lau via llvm-commits
- [clang] [llvm] Enable fexec-charset option (PR #138895)
Abhina Sree via llvm-commits
- [llvm] Revert "[Hexagon] Handle subreg copies between DoubleRegs and IntRegs… (PR #182861)
Brian Cain via llvm-commits
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Archived on: Sat Feb 28 22:11:18 PST 2026
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