[llvm] [RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (PR #183657)

[Craig Topper via llvm-commits]

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@@ -95,6 +104,21 @@ bool RISCVMoveMerge::isRegisterEven(const DestSourcePair &RegPair) {
   return SrcPair.isValid() && DestPair.isValid();
 }
 
+bool RISCVMoveMerge::isRegisterOdd(const DestSourcePair &RegPair) {
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topperc wrote:

This function and isRegisterEven are misnamed. There are 2 registers involved. Maybe `isOddRegisterCopy`?

https://github.com/llvm/llvm-project/pull/183657