[llvm] [DAG] Improved handling of ISD::ROTL and ISD::ROTR in isKnownToBeAPowerOfTwo (PR #182744)

[Simon Pilgrim via llvm-commits]

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@@ -889,3 +891,32 @@ define i1 @pow2_and_i128(i128 %num, i128 %shift) {
   %bool = icmp eq i128 %bit, 0
   ret i1 %bool
 }
+
+define <2 x i32> @pow2_rotl_vec() {
+; CHECK-LABEL: pow2_rotl_vec:
+; CHECK:       # %bb.0:
+; CHECK:       xmm0 = [32,0,0,0]
+; CHECK:       retq
+entry:
+  ; build vector <4,0>
+  %v0 = insertelement <2 x i32> zeroinitializer, i32 4, i32 0
+  %v1 = insertelement <2 x i32> %v0, i32 0, i32 1
+  %amt0 = insertelement <2 x i32> zeroinitializer, i32 3, i32 0
+  %amt1 = insertelement <2 x i32> %amt0, i32 3, i32 1
+  %r = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %v1, <2 x i32> %v1, <2 x i32> %amt1)
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @pow2_rotr_vec() {
+; CHECK-LABEL: pow2_rotr_vec:
+; CHECK:       # %bb.0:
+; CHECK:       xmm0 = [2147483648,0,0,0]
+; CHECK:       retq
+entry:
+  %v0 = insertelement <2 x i32> zeroinitializer, i32 16, i32 0
+  %v1 = insertelement <2 x i32> %v0, i32 0, i32 1
+  %amt0 = insertelement <2 x i32> zeroinitializer, i32 5, i32 0
+  %amt1 = insertelement <2 x i32> %amt0, i32 5, i32 1
+  %r = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %v1, <2 x i32> %v1, <2 x i32> %amt1)
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RKSimon wrote:

Take a look at #183924 - that shows how we can use DemandedElts properly for vectors

https://github.com/llvm/llvm-project/pull/182744