[llvm] [WebAssembly] Optimize legalized vector multiplications into i32x4.dot_i16x8_s (PR #183244)

[Sam Parker via llvm-commits]

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@@ -3714,6 +3715,127 @@ SDValue performConvertFPCombine(SDNode *N, SelectionDAG &DAG) {
   return SDValue();
 }
 
+// We are looking for patterns that represent a widened arithmetic operation
+// followed by a pairwise addition. This perfectly matches the semantics of
+// the WebAssembly i32x4.dot_i16x8_s instruction.
+//
+// Step 1. Widened arithmetic operation (8 lanes)
+// We match the following variations for 't' (v8i32):
+//  - Var * Var:    t = mul (sign_extend (v8i16 x0)), (sign_extend (v8i16 x1))
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sparker-arm wrote:

> When the original code contains a multiplication by a power-of-2 constant, the generic combiner automatically transforms that MUL into a SHL

Right, so why don't we handle this separately when we do our mul combining? You doing something very specific here, and if the 'muls' feed a sub, for instance, then we'll achieve nothing with this code. If we can generate an extmul, instead of a shl and extend, then we should do that and, hopefully, the existing tablegen patterns will handle the dot matching.

Or am I still missing something here?

https://github.com/llvm/llvm-project/pull/183244