[llvm] AMDGPU: Add FlatSignedOffset feature and use it for flat offset printing (PR #183483)

[Mariusz Sikora via llvm-commits]

https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/183483

>From 523cb52f461a56901b2bdcaba901891557278e36 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Thu, 26 Feb 2026 04:13:09 -0500
Subject: [PATCH 1/2] AMDGPU: Add FlatSignedOffset feature and use it for flat
 offset printing

---
 llvm/lib/Target/AMDGPU/AMDGPU.td                          | 7 ++++++-
 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 2 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index eee33dbeea022..0fc3715447822 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1097,6 +1097,10 @@ defm SWakeupBarrier : AMDGPUSubtargetFeature<"s-wakeup-barrier-inst",
   "Has s_wakeup_barrier instruction."
 >;
 
+defm FlatSignedOffset : AMDGPUSubtargetFeature<"flat-signed-offset",
+  "Has signed flat offsets."
+>;
+
 //===------------------------------------------------------------===//
 // Subtarget Features (options and debugging)
 //===------------------------------------------------------------===//
@@ -1460,7 +1464,8 @@ def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
    FeatureDefaultComponentBroadcast, FeatureMaxHardClauseLength32,
    FeatureAtomicFMinFMaxF32GlobalInsts, FeatureAtomicFMinFMaxF32FlatInsts,
    FeatureIEEEMinimumMaximumInsts, FeatureMinimum3Maximum3F32,
-   FeatureMinimum3Maximum3F16, FeatureAgentScopeFineGrainedRemoteMemoryAtomics
+   FeatureMinimum3Maximum3F16, FeatureAgentScopeFineGrainedRemoteMemoryAtomics,
+   FeatureFlatSignedOffset
   ]
 >;
 
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 66792a67503d8..8c54d292dbd1c 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -130,7 +130,7 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     bool AllowNegative = (Desc.TSFlags & (SIInstrFlags::FlatGlobal |
                                           SIInstrFlags::FlatScratch)) ||
-                         AMDGPU::isGFX12(STI);
+                         STI.hasFeature(AMDGPU::FeatureFlatSignedOffset);
 
     if (AllowNegative) // Signed offset
       O << formatDec(SignExtend32(Imm, AMDGPU::getNumFlatOffsetBits(STI)));

>From 014f73c45a02d98a0b5c6ba8e5914497edf494af Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Thu, 26 Feb 2026 14:00:59 +0100
Subject: [PATCH 2/2] Update llvm/lib/Target/AMDGPU/AMDGPU.td

Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
---
 llvm/lib/Target/AMDGPU/AMDGPU.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 0fc3715447822..c02ee7f17ea17 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1098,7 +1098,7 @@ defm SWakeupBarrier : AMDGPUSubtargetFeature<"s-wakeup-barrier-inst",
 >;
 
 defm FlatSignedOffset : AMDGPUSubtargetFeature<"flat-signed-offset",
-  "Has signed flat offsets."
+  "Immediate offset of FLAT instructions are always signed"
 >;
 
 //===------------------------------------------------------------===//