[llvm-branch-commits] [RISC-V][MC][RVY] Add support for RVY loads/stores (PR #177073)

[Alexander Richardson via llvm-branch-commits]

================
@@ -235,10 +235,12 @@ def GPRMemZeroOffset : MemOperand<GPR> {
 }
 
 def GPRMem : MemOperand<GPR>;
-
+def BasePtr : MemOperand<BasePtrRegClass>;
----------------
arichardson wrote:

In the future all uses of GPRMem should be migrated to BasePtr, but completing the full migration will require a few more tablegen improvements. I was hoping to do this in multiple steps.

For example the following error would need https://github.com/llvm/llvm-project/pull/203599:
```
RISCVInstrInfoXqci.td:1277:3: error: in argument #1: argument register class GPR is not a subclass of operand register class BasePtrRegClass
  def  : InstAlias<"qc.e.lb  $rd, (${rs1})",
```

https://github.com/llvm/llvm-project/pull/177073