[llvm-branch-commits] [RISC-V][MC][RVY] Add support for RVY loads/stores (PR #177073)

[Alexander Richardson via llvm-branch-commits]

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@@ -199,6 +199,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   ParseStatus parseRegister(OperandVector &Operands, bool AllowParens = false);
   ParseStatus parseMemOpBaseReg(OperandVector &Operands);
   ParseStatus parseZeroOffsetMemOp(OperandVector &Operands);
+  ParseStatus parseStackPtr(OperandVector &Operands);
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arichardson wrote:

left over from previous version of this patch set, thanks for noting. 

https://github.com/llvm/llvm-project/pull/177073