[llvm-branch-commits] [RISC-V][MC][RVY] Add support for RVY loads/stores (PR #177073)

[Alexander Richardson via llvm-branch-commits]

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@@ -235,10 +235,12 @@ def GPRMemZeroOffset : MemOperand<GPR> {
 }
 
 def GPRMem : MemOperand<GPR>;
-
+def BasePtr : MemOperand<BasePtrRegClass>;
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arichardson wrote:

Actually it looks like this can be solved quite easily and we can remove this part of the diff.

https://github.com/llvm/llvm-project/pull/177073