[llvm-branch-commits] [llvm] e2e4b92 - Vector implementation
Amy Kwan via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Sep 2 09:09:28 PDT 2022
Author: Amy Kwan
Date: 2022-09-02T11:08:45-05:00
New Revision: e2e4b924e40d796c067917feafadbe2401ea5c5f
URL: https://github.com/llvm/llvm-project/commit/e2e4b924e40d796c067917feafadbe2401ea5c5f
DIFF: https://github.com/llvm/llvm-project/commit/e2e4b924e40d796c067917feafadbe2401ea5c5f.diff
LOG: Vector implementation
Added:
Modified:
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
index 270a8c9e6757..476d2d2f2dcf 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
@@ -113,6 +113,8 @@ bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
SmallVector<ArgInfo, 8> SplitArgs;
unsigned I = 0;
for (const auto &Arg : F.args()) {
+ fprintf(stderr, "AKWAN - in lowerFormalArguments() - Dumping arguments\n");
+ Arg.dump();
if (DL.getTypeStoreSize(Arg.getType()).isZero())
continue;
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
index 63ea629825c8..bc3109cad01e 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -20,6 +20,8 @@ RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
{0, 32, PPC::FPRRegBank},
// 2: FPR 64-bit value
{0, 64, PPC::FPRRegBank},
+ // 3: VSX 128-bit vector
+ {0, 128, PPC::VSXRegBank}
};
// ValueMappings.
@@ -49,6 +51,10 @@ RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
{&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+ // 5: VSX 128-bit vector.
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
};
// TODO Too simple!
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index 62a5b001b31c..eddfe36b165b 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -91,6 +91,11 @@ static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
if (Ty.getSizeInBits() == 64)
return &PPC::F8RCRegClass;
}
+ if (RB->getID() == PPC::VSXRegBankID) {
+ if (Ty.getSizeInBits() == 128)
+ //return &PPC::VSRCRegClass;
+ return &PPC::VRRCRegClass;
+ }
llvm_unreachable("Unknown RegBank!");
}
@@ -224,6 +229,9 @@ bool PPCInstructionSelector::select(MachineInstr &I) {
auto &MF = *MBB.getParent();
auto &MRI = MF.getRegInfo();
+ fprintf(stderr, "AKWAN - Global ISel begins:\n");
+ I.dump();
+
if (!isPreISelGenericOpcode(I.getOpcode())) {
if (I.isCopy())
return selectCopy(I, TII, MRI, TRI, RBI);
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
index a6dafdea3086..e6b52af13f56 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -23,6 +23,10 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
const LLT S16 = LLT::scalar(16);
const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64);
+ const LLT V16S8 = LLT::fixed_vector(16, 8);
+ const LLT V8S16 = LLT::fixed_vector(8, 16);
+ //const LLT V4S32 = LLT::fixed_vector(4, 32);
+ //const LLT V2S64 = LLT::fixed_vector(2, 64);
getActionDefinitionsBuilder(G_IMPLICIT_DEF).legalFor({S64});
getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({S64})
@@ -35,7 +39,7 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
getActionDefinitionsBuilder(G_SEXT_INREG)
.legalForTypeWithAnyImm({S64});
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
- .legalFor({S64})
+ .legalFor({S64, V16S8, V8S16})
.clampScalar(0, S64, S64);
getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({S64})
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index a9fb1ade5f95..206ff2e955ad 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -12,6 +12,7 @@
#include "PPCRegisterBankInfo.h"
#include "PPCRegisterInfo.h"
+#include "PPCSubtarget.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
@@ -47,6 +48,10 @@ PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
case PPC::VSSRCRegClassID:
case PPC::F4RCRegClassID:
return getRegBank(PPC::FPRRegBankID);
+ case PPC::VSRCRegClassID:
+ case PPC::VRRCRegClassID:
+ case PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID:
+ return getRegBank(PPC::VSXRegBankID);
default:
llvm_unreachable("Unexpected register class");
}
@@ -90,7 +95,7 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_TRUNC:
assert(NumOperands <= 3 &&
"This code is for instructions with 3 or less operands");
- OperandsMapping = getValueMapping(PMI_GPR64);
+ OperandsMapping = getValueMapping(MF.getSubtarget<PPCSubtarget>().hasAltivec() ? PMI_VSX128 : PMI_GPR64);
break;
case TargetOpcode::G_SEXT_INREG:
OperandsMapping = getOperandsMapping(
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
index 40959a3e625e..883dfa3f3c59 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
@@ -31,6 +31,7 @@ class PPCGenRegisterBankInfo : public RegisterBankInfo {
PMI_GPR64 = 1,
PMI_FPR32 = 2,
PMI_FPR64 = 3,
+ PMI_VSX128 = 4,
PMI_Min = PMI_GPR64,
};
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
index ad87bebf5170..5ed390d70d5f 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
@@ -15,3 +15,6 @@
def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
/// Float point Registers
def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
+/// VSX Vector Registers
+//def VSXRegBank : RegisterBank<"VSX", [VSRC]>;
+def VSXRegBank : RegisterBank<"VSX", [VRRC]>;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8843bd8cae8a..1f95cac66adc 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -18045,7 +18045,7 @@ CCAssignFn *PPCTargetLowering::ccAssignFnForCall(CallingConv::ID CC,
case CallingConv::Cold:
return (Return ? RetCC_PPC_Cold : CC_PPC64_ELF_FIS);
default:
- return CC_PPC64_ELF_FIS;
+ return RetCC_PPC;
}
}
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