[llvm-branch-commits] [llvm] 4da2e94 - FP Patch by Western
Amy Kwan via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Sep 2 09:09:27 PDT 2022
Author: Amy Kwan
Date: 2022-09-01T10:48:52-05:00
New Revision: 4da2e948311280fe0fe0d9845a5e9c12c056fb92
URL: https://github.com/llvm/llvm-project/commit/4da2e948311280fe0fe0d9845a5e9c12c056fb92
DIFF: https://github.com/llvm/llvm-project/commit/4da2e948311280fe0fe0d9845a5e9c12c056fb92.diff
LOG: FP Patch by Western
Added:
llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll
Modified:
llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
index 471af5d13d80..63ea629825c8 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -16,6 +16,10 @@ RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
/* StartIdx, Length, RegBank */
// 0: GPR 64-bit value.
{0, 64, PPC::GPRRegBank},
+ // 1: FPR 32-bit value
+ {0, 32, PPC::FPRRegBank},
+ // 2: FPR 64-bit value
+ {0, 64, PPC::FPRRegBank},
};
// ValueMappings.
@@ -37,6 +41,14 @@ RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
{&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
{&PPCGenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
+ // 2: FPR 32-bit value.
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
+ // 3: FPR 64-bit value.
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
+ {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
};
// TODO Too simple!
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index f44a22308496..62a5b001b31c 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -80,18 +80,45 @@ PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,
{
}
+static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
+ if (RB->getID() == PPC::GPRRegBankID) {
+ if (Ty.getSizeInBits() == 64)
+ return &PPC::G8RCRegClass;
+ }
+ if (RB->getID() == PPC::FPRRegBankID) {
+ if (Ty.getSizeInBits() == 32)
+ return &PPC::F4RCRegClass;
+ if (Ty.getSizeInBits() == 64)
+ return &PPC::F8RCRegClass;
+ }
+
+ llvm_unreachable("Unknown RegBank!");
+}
+
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) {
Register DstReg = I.getOperand(0).getReg();
Register SrcReg = I.getOperand(1).getReg();
- if (!Register::isPhysicalRegister(DstReg))
- if (!RBI.constrainGenericRegister(DstReg, PPC::G8RCRegClass, MRI))
+ if (!Register::isPhysicalRegister(DstReg)) {
+ const TargetRegisterClass *RC =
+ getRegClass(MRI.getType(DstReg), RBI.getRegBank(DstReg, MRI, TRI));
+ if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
+ LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+ << " dest operand\n");
return false;
- if (!Register::isPhysicalRegister(SrcReg))
- if (!RBI.constrainGenericRegister(SrcReg, PPC::G8RCRegClass, MRI))
+ }
+ }
+ if (!Register::isPhysicalRegister(SrcReg)) {
+ const TargetRegisterClass *RC =
+ getRegClass(MRI.getType(SrcReg), RBI.getRegBank(SrcReg, MRI, TRI));
+ if (!RBI.constrainGenericRegister(SrcReg, *RC, MRI)) {
+ LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+ << " source operand\n");
return false;
+ }
+ }
return true;
}
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
index 903ccb4dcd80..a6dafdea3086 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -40,5 +40,9 @@ PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({S64})
.clampScalar(0, S64, S64);
+
+ getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
+ .legalFor({S32, S64});
+
getLegacyLegalizerInfo().computeTables();
}
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index 575d4d4d125a..a9fb1ade5f95 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -38,6 +38,15 @@ PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
case PPC::G8pRCRegClassID:
case PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID:
return getRegBank(PPC::GPRRegBankID);
+ case PPC::VSFRCRegClassID:
+ case PPC::SPILLTOVSRRC_and_VSFRCRegClassID:
+ case PPC::SPILLTOVSRRC_and_VFRCRegClassID:
+ case PPC::SPILLTOVSRRC_and_F4RCRegClassID:
+ case PPC::F8RCRegClassID:
+ case PPC::VFRCRegClassID:
+ case PPC::VSSRCRegClassID:
+ case PPC::F4RCRegClassID:
+ return getRegBank(PPC::FPRRegBankID);
default:
llvm_unreachable("Unexpected register class");
}
@@ -49,8 +58,7 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// Try the default logic for non-generic instructions that are either copies
// or already have some operands assigned to banks.
- if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
- Opc == TargetOpcode::G_PHI) {
+ if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
const RegisterBankInfo::InstructionMapping &Mapping =
getInstrMappingImpl(MI);
if (Mapping.isValid())
@@ -88,26 +96,23 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OperandsMapping = getOperandsMapping(
{getValueMapping(PMI_GPR64), getValueMapping(PMI_GPR64), nullptr});
break;
- case TargetOpcode::G_CONSTANT:
- OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
- break;
- case TargetOpcode::COPY: {
- Register DstReg = MI.getOperand(0).getReg();
+ case TargetOpcode::G_FADD:
+ case TargetOpcode::G_FSUB:
+ case TargetOpcode::G_FMUL:
+ case TargetOpcode::G_FDIV: {
Register SrcReg = MI.getOperand(1).getReg();
- const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI);
- const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI);
- if (!DstRB)
- DstRB = SrcRB;
- else if (!SrcRB)
- SrcRB = DstRB;
- assert(DstRB && SrcRB && "Both RegBank were nullptr");
- unsigned Size = getSizeInBits(DstReg, MRI, TRI);
- Cost = copyCost(*DstRB, *SrcRB, Size);
- OperandsMapping = getCopyMapping(DstRB->getID(), SrcRB->getID(), Size);
- // We only care about the mapping of the destination.
- NumOperands = 1;
+ unsigned Size = getSizeInBits(SrcReg, MRI, TRI);
+
+ assert((Size == 32 || Size == 64) && "Unsupport float point types!\n");
+ if (Size == 32)
+ OperandsMapping = getValueMapping(PMI_FPR32);
+ else
+ OperandsMapping = getValueMapping(PMI_FPR64);
break;
}
+ case TargetOpcode::G_CONSTANT:
+ OperandsMapping = getOperandsMapping({getValueMapping(PMI_GPR64), nullptr});
+ break;
default:
return getInvalidInstructionMapping();
}
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
index 11bdd98cd3b5..40959a3e625e 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
@@ -29,6 +29,8 @@ class PPCGenRegisterBankInfo : public RegisterBankInfo {
enum PartialMappingIdx {
PMI_None = -1,
PMI_GPR64 = 1,
+ PMI_FPR32 = 2,
+ PMI_FPR64 = 3,
PMI_Min = PMI_GPR64,
};
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
index 771d33e9f3a3..ad87bebf5170 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
@@ -13,3 +13,5 @@
/// General Purpose Registers
def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
+/// Float point Registers
+def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
diff --git a/llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll b/llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll
new file mode 100644
index 000000000000..5bd8eaad61fa
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -global-isel -o - < %s | FileCheck %s
+
+define float @float_add(float %a, float %b) {
+; CHECK-LABEL: float_add:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xsaddsp 1, 1, 2
+; CHECK-NEXT: blr
+entry:
+ %add = fadd float %a, %b
+ ret float %add
+}
+
+define double @double_add(double %a, double %b) {
+; CHECK-LABEL: double_add:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xsadddp 1, 1, 2
+; CHECK-NEXT: blr
+entry:
+ %add = fadd double %a, %b
+ ret double %add
+}
+
+define float @float_sub(float %a, float %b) {
+; CHECK-LABEL: float_sub:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xssubsp 1, 1, 2
+; CHECK-NEXT: blr
+entry:
+ %sub = fsub float %a, %b
+ ret float %sub
+}
+
+define float @float_mul(float %a, float %b) {
+; CHECK-LABEL: float_mul:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xsmulsp 1, 1, 2
+; CHECK-NEXT: blr
+entry:
+ %mul = fmul float %a, %b
+ ret float %mul
+}
+
+define float @float_div(float %a, float %b) {
+; CHECK-LABEL: float_div:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xsdivsp 1, 1, 2
+; CHECK-NEXT: blr
+entry:
+ %div = fdiv float %a, %b
+ ret float %div
+}
More information about the llvm-branch-commits
mailing list