[llvm-branch-commits] [llvm] d905af0 - Update naming

[Amy Kwan via llvm-branch-commits]

Author: Amy Kwan
Date: 2022-09-02T15:21:45-05:00
New Revision: d905af0392054dd4c5e9beb1960eae9477b9a181

URL: https://github.com/llvm/llvm-project/commit/d905af0392054dd4c5e9beb1960eae9477b9a181
DIFF: https://github.com/llvm/llvm-project/commit/d905af0392054dd4c5e9beb1960eae9477b9a181.diff

LOG: Update naming

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
    llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
    llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
    llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
    llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
index bc3109cad01e9..1765fa0be0b1b 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
+++ b/llvm/lib/Target/PowerPC/GISel/PPCGenRegisterBankInfo.def
@@ -20,8 +20,8 @@ RegisterBankInfo::PartialMapping PPCGenRegisterBankInfo::PartMappings[]{
     {0, 32, PPC::FPRRegBank},
     // 2: FPR 64-bit value
     {0, 64, PPC::FPRRegBank},
-    // 3: VSX 128-bit vector
-    {0, 128, PPC::VSXRegBank}
+    // 3: 128-bit vector
+    {0, 128, PPC::VECRegBank} // VSX
 };
 
 // ValueMappings.
@@ -52,9 +52,9 @@ RegisterBankInfo::ValueMapping PPCGenRegisterBankInfo::ValMappings[]{
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     {&PPCGenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
     // 5: VSX 128-bit vector.
-    {&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
-    {&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
-    {&PPCGenRegisterBankInfo::PartMappings[PMI_VSX128 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_VEC128 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_VEC128 - PMI_Min], 1},
+    {&PPCGenRegisterBankInfo::PartMappings[PMI_VEC128 - PMI_Min], 1},
 };
 
 // TODO Too simple!

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
index eddfe36b165bf..4e186820803bd 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
@@ -91,7 +91,7 @@ static const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank *RB) {
     if (Ty.getSizeInBits() == 64)
       return &PPC::F8RCRegClass;
   }
-  if (RB->getID() == PPC::VSXRegBankID) {
+  if (RB->getID() == PPC::VECRegBankID) {
     if (Ty.getSizeInBits() == 128)
       //return &PPC::VSRCRegClass;
       return &PPC::VRRCRegClass;

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
index 206ff2e955ad6..1239c77acf447 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -51,7 +51,7 @@ PPCRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   case PPC::VSRCRegClassID:
   case PPC::VRRCRegClassID:
   case PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID:
-    return getRegBank(PPC::VSXRegBankID);
+    return getRegBank(PPC::VECRegBankID);
   default:
     llvm_unreachable("Unexpected register class");
   }
@@ -95,7 +95,7 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_TRUNC:
     assert(NumOperands <= 3 &&
            "This code is for instructions with 3 or less operands");
-    OperandsMapping = getValueMapping(MF.getSubtarget<PPCSubtarget>().hasAltivec() ? PMI_VSX128 : PMI_GPR64);
+    OperandsMapping = getValueMapping(MF.getSubtarget<PPCSubtarget>().hasAltivec() ? PMI_VEC128 : PMI_GPR64);
     break;
   case TargetOpcode::G_SEXT_INREG:
     OperandsMapping = getOperandsMapping(

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
index 883dfa3f3c597..0aa126dfcf8c5 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
@@ -31,7 +31,7 @@ class PPCGenRegisterBankInfo : public RegisterBankInfo {
     PMI_GPR64 = 1,
     PMI_FPR32 = 2,
     PMI_FPR64 = 3,
-    PMI_VSX128 = 4,
+    PMI_VEC128 = 4,
     PMI_Min = PMI_GPR64,
   };
 

diff  --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
index 5ed390d70d5f1..a1153dae140f1 100644
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
@@ -15,6 +15,5 @@
 def GPRRegBank : RegisterBank<"GPR", [G8RC, G8RC_NOX0]>;
 /// Float point Registers
 def FPRRegBank : RegisterBank<"FPR", [VSSRC]>;
-/// VSX Vector Registers
-//def VSXRegBank : RegisterBank<"VSX", [VSRC]>;
-def VSXRegBank : RegisterBank<"VSX", [VRRC]>;
+/// Vector Registers
+def VECRegBank : RegisterBank<"VEC", [VSRC]>;