[llvm-branch-commits] [cfe-branch] r368420 - Merging r367403:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Fri Aug  9 02:40:09 2019
New Revision: 368420

URL: http://llvm.org/viewvc/llvm-project?rev=368420&view=rev
Log:
Merging r367403:
------------------------------------------------------------------------
r367403 | lenary | 2019-07-31 11:45:55 +0200 (Wed, 31 Jul 2019) | 20 lines

[RISCV] Support 'f' Inline Assembly Constraint

Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.

Reviewers: asb, lewis-revill

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65500
------------------------------------------------------------------------

Modified:
    cfe/branches/release_90/   (props changed)
    cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp
    cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c

Propchange: cfe/branches/release_90/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Aug  9 02:40:09 2019
@@ -1,4 +1,4 @@
 /cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:366429,366448,366457,366474,366480,366483,366511,366670,366694,366699,366878,367008,367039,367055,367103,367134,367301,367305,367323,367387,367520,367530,367661,367675,367823,367906
+/cfe/trunk:366429,366448,366457,366474,366480,366483,366511,366670,366694,366699,366878,367008,367039,367055,367103,367134,367301,367305,367323,367387,367403,367520,367530,367661,367675,367823,367906
 /cfe/trunk/test:170344
 /cfe/trunk/test/SemaTemplate:126920

Modified: cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp?rev=368420&r1=368419&r2=368420&view=diff
==============================================================================
--- cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/branches/release_90/lib/Basic/Targets/RISCV.cpp Fri Aug  9 02:40:09 2019
@@ -56,6 +56,10 @@ bool RISCVTargetInfo::validateAsmConstra
     // A 5-bit unsigned immediate for CSR access instructions.
     Info.setRequiresImmediate(0, 31);
     return true;
+  case 'f':
+    // A floating-point register.
+    Info.setAllowsRegister();
+    return true;
   }
 }
 

Modified: cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c?rev=368420&r1=368419&r2=368420&view=diff
==============================================================================
--- cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c (original)
+++ cfe/branches/release_90/test/CodeGen/riscv-inline-asm.c Fri Aug  9 02:40:09 2019
@@ -26,3 +26,15 @@ void test_K() {
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+float f;
+double d;
+void test_f() {
+// CHECK-LABEL: define void @test_f()
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
+// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
+  asm volatile ("" :: "f"(f));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d
+// CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
+  asm volatile ("" :: "f"(d));
+}